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The HUAWEI ARM Business Suspension - How Bad Is This?

The HUAWEI ARM Business Suspension – How Bad Is This?

BBC just revealed that HUAWEI ARM business partnership has also been suspended. Find out what this new development means for HUAWEI, and consumers!

 

HUAWEI ARM Business Suspended

ARM instructed their employees to suspend business with HUAWEI on 16 May 2019, according to internal documents obtained by the BBC.

Specifically, they were told to halt “all active contracts, support entitlements, and any pending engagements” with HUAWEI and its subsidiaries because they were added to the US Entity List.

 

How Is ARM Affected By The US Entity List?

ARM is a UK-based company, owned by Japanese conglomerate Softbank, and is thus not directly subject to the HUAWEI Trump ban.

However, they said that their designs contained “US origin technology“, which would subject them to the US government restrictions.

 

What About The Temporary Licence?

The temporary 90-day licence does not apply to ARM, because it only permits software patches and bug fixes for consumer devices, and network equipment.

Recommended : The HUAWEI Trump Ban – Everything You Need To Know!

 

What Does ARM Do For HUAWEI?

ARM designs the processor and graphics cores that power almost all mobile SoCs used in smartphones today.

Whether your smartphone uses the Apple A11, a Qualcomm Snapdragon, or a Samsung Exynos mobile SoC – most are built around the ARM Cortex processor and/or ARM Mali graphics cores.

HUAWEI relies on ARM designs and licences for their Hisilicon Kirin mobile SoCs, like the Kirin 980 that powers their new HUAWEI P30 Pro smartphone.

 

The HUAWEI ARM Business Suspension – How Bad Is This?

Consumers : No Effect

Let’s get this straight, because there are people wondering if their HUAWEI smartphones will stop working. There are even people trying to sell off their HUAWEI smartphones in panic.

Seriously – this has NO EFFECT on all current HUAWEI and HONOR smartphones. Even future HUAWEI and HONOR models that will come out this year are unlikely to be affected in any way.

Short- to Medium-Term : No Real Damage To HUAWEI

In the short- to medium-term, the damage is more perception than substance.

  • HUAWEI can continue to manufacture and use their existing ARM-based designs, including the recently announced Kunpeng 920 server processors and Tiangang 5G processor.
  • HUAWEI can manufacture completed ARM-based designs that have not been launched, including their upcoming Kirin 985 flagship processor.
  • HUAWEI will be able to produce new smartphones, servers and other devices that use those ARM-based processors.

Long-Term : Potentially Disastrous For HUAWEI

The HUAWEI ARM licences and technical support are critical for the development of future mobile and server processors.

It would take them a long time, and a lot of effort, to switch to an alternative RISC architecture, like the open-source RISC-V.

Their best bet would be to temporarily suspend or slow down the development of their next-generation ARM-based designs, while the US and Chinese government “duke it out”…

 

How Will This Work Out?

President Donald Trump has framed HUAWEI as a national security threat, but the HUAWEI Trump ban is really about the trade war with China.

Placing HUAWEI in the Entity List prevents HUAWEI from buying American products and technology, not sell their products and technology to American companies.

In fact, HUAWEI does not even sell their smartphones or laptops in the United States, which begs the question – why on earth were they even targeted?

Photo Credit : News.com.au

In all likelihood, Trump is hoping that tightening the noose around HUAWEI will force Chinese President Xi Jinping into a trade deal.

We believe this ban will eventually resolve in a US-Chinese trade deal of some sort… The alternative – open conflict – would, frankly, be quite unthinkable.

 

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Three New Western Digital RISC-V Developments Revealed!

Western Digital just announced three new open-source innovations to support its internal RISC-V SweRV Core development efforts and those of the growing RISC-V ecosystem. Learn more about Western Digital’s latest RISC-V move right here!

 

The New Western Digital RISC-V Developments

Western Digital’s Chief Technology Officer Martin Fink unveiled plans to release a new open source RISC-V core, an open standard initiative for cache-coherent memory over a network and an open source RISC-V instruction set simulator.

These innovations are expected to accelerate development of new open, purpose-built compute architectures for Big Data and Fast Data environments. Western Digital has taken an active role in helping to advance the RISC-V ecosystem.

This includes multiple related strategic investments and partnerships. Western Digital has also demonstrated progress toward its stated goal of transitioning one billion of the company’s processor cores to the RISC-V architecture.

“As Big Data and Fast Data continues to proliferate, purpose-built technologies are essential for unlocking the true value of data across today’s wide-ranging data-centric applications,” said Fink.

“Our SweRV Core and the new cache coherency fabric initiative demonstrate the significant possibilities that can be realized by bringing data closer to processing power.”

“These planned contributions to the open-source community and continued commitment of the RISC-V initiative offer exciting potential to accelerate collaborative innovation and data-driven discoveries.”

 

What Is RISC-V?

RISC-V is an open, scalable instruction set architecture that enables the diversity of Big Data and Fast Data applications and workloads proliferating in core data centers and in remote and mobile systems at the edge.

As an alternative to current, standard, general purpose compute architectures, RISC-V can be utilized to enable specialty processing, memory centric solutions, unique storage and flexible interconnect applications.

Western Digital is planning to open source its new RISC-V SweRV Core, which has a 2-way superscalar design. Western Digital’s RISC-V SweRV Core is a 32-bit, 9-stage pipeline core that allows several instructions to be loaded at once and execute simultaneously, shortening the time taken to run programs.

It is a compact, in-order core and runs at 4.9 CoreMarks/MHz. Its power-efficient design offers clock speeds of up to 1.8 GHz on a 28 nm CMOS process technology. The company plans to use the RISC-V SweRV Core in various internal embedded designs like flash controllers and SSDs.

Open sourcing the core is expected to drive development of new data-centric applications such as Internet of Things (IoT), secure processing, industrial controls and more.

 

OmniXtend

Western Digital’s OmniXtend is a new open approach to providing cache coherent memory over an Ethernet fabric. This memory-centric system architecture provides open standard interfaces for access and data sharing across processors, machine learning accelerators, GPUs, FPGAs and other components.

It is an open solution for efficiently attaching persistent memory to processors and offers potential support of future advanced fabrics that connect compute, storage, memory and I/O components.

 

SweRV Instruction Set Simulator (ISS)

Also introduced was its open-sourced SweRV Instruction Set Simulator (ISS) which offers full test bench support for use with RISC-V cores.

An ISS is a computer program that simulates the execution of instructions of a processor. It allows external events to be modeled, such as interrupts and bus errors, and assures the RISC-V core is functioning properly.

The company utilized the SweRV ISS to rigorously simulate and validate the SweRV Core with more than 10 billion instructions executed. Western Digital expects both the SweRV Core and SweRV ISS will help to accelerate the industry’s move to an open source instruction set architecture.

“Speeds, feeds, and brute compute is no longer the winning formula for edge and endpoint computing. As more data moves to the edge for real-time processing and inferencing, configurable architectures will be better suited to meet the needs of heavy and often dynamic application workloads, especially for those driven by artificial intelligence and Internet of Things,” said Mario Morales, program vice president, enabling technologies and semiconductors, IDC. “Power efficiency, configurability, and low power will become the key metrics for edge and endpoint computing architectures.”

 

Availability + Resources

Western Digital’s SweRV ISS and OmniXtend architecture are available now for download at the following locations:

Western Digital’s RISC-V SweRV Core will be available in CY Q1 2019.

 

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