Tag Archives: PCI Controller

Master Priority Rotation from The Tech ARP BIOS Guide!

Master Priority Rotation from The Tech ARP BIOS Guide!

Master Priority Rotation

Common Options : 1 PCI, 2 PCI, 3 PCI

 

Quick Review of Master Priority Rotation

The Master Priority Rotation BIOS feature controls the priority of the processor’s accesses to the PCI bus.

If you choose 1 PCI, the processor will always be granted access right after the current PCI bus master completes its transaction, irrespective of how many other PCI bus masters are on the queue.

If you choose 2 PCI, the processor will always be granted access right after the second PCI bus master on the queue completes its transaction.

If you choose 3 PCI, the processor will always be granted access right after the third PCI bus master on the queue completes its transaction.

But no matter what you choose, the processor is guaranteed access to the PCI bus after a certain number of PCI bus master grants.

It doesn’t matter if there are numerous PCI bus masters on the queue or when the processor requests access to the PCI bus. The processor will always be granted access after one PCI bus master transaction (1 PCI), two transactions (2 PCI) or three transactions (3 PCI).

For better overall performance, it is recommended that you select the 1 PCI option as this allows the processor to access the PCI bus with minimal delay.

However, if you wish to improve the performance of your PCI devices, you can try the 2 PCI or 3 PCI options. They ensure that your PCI cards will receive greater PCI bus priority.

Details of Master Priority Rotation

The Master Priority Rotation BIOS feature controls the priority of the processor’s accesses to the PCI bus.

If you choose 1 PCI, the processor will always be granted access right after the current PCI bus master completes its transaction, irrespective of how many other PCI bus masters are on the queue. This improves processor-to-PCI performance, at the expense of other PCI transactions.

If you choose 2 PCI, the processor will always be granted access right after the second PCI bus master on the queue completes its transaction. This means the processor has to wait for just two PCI bus masters to complete their transactions on the PCI bus before it can gain access to the PCI bus itself. This means slightly poorer processor-to-PCI performance but PCI bus masters will enjoy slightly better performance.

If you choose 3 PCI, the processor will always be granted access right after the third PCI bus master on the queue completes its transaction. This means the processor has to wait for three PCI bus masters to complete their transactions on the PCI bus before it can gain access to the PCI bus itself. This means poorer processor-to-PCI performance but PCI bus masters will enjoy better performance.

But no matter what you choose, the processor is guaranteed access to the PCI bus after a certain number of PCI bus master grants.

It doesn’t matter if there are numerous PCI bus masters on the queue or when the processor requests access to the PCI bus. The processor will always be granted access after one PCI bus master transaction (1 PCI), two transactions (2 PCI) or three transactions (3 PCI).

For better overall performance, it is recommended that you select the 1 PCI option as this allows the processor to access the PCI bus with minimal delay.

However, if you wish to improve the performance of your PCI devices, you can try the 2 PCI or 3 PCI options. They ensure that your PCI cards will receive greater PCI bus priority.

 

Recommended Reading

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PCI Clock Synchronization Mode – The Tech ARP BIOS Guide

PCI Clock Synchronization Mode

Common Options : To CPU, 33.33 MHz, Auto

 

Quick Review of PCI Clock Synchronization Mode

The PCI Clock Synchronization Mode BIOS feature allows you to force the PCI bus to either synchronize itself with the processor FSB (Front Side Bus) speed, or run at the standard clock speed of 33.33 MHz.

When set to To CPU, the PCI bus speed is slaved to the processor’s FSB speed. Any change in FSB speed will result in a similar change in the PCI bus speed. For example, if you increase the processor’s FSB speed by 10%, the PCI bus speed will increase by 10% as well.

When set to 33.33 MHz, the PCI bus speed will be locked into its standard clock speed of 33.33 MHz. No matter what the processor’s FSB speed is, the PCI bus will always run at 33.33 MHz.

The Auto option is ambiguous. Without testing, its effect cannot be ascertained since it’s up to the manufacturer what it wishes to implement by default for the motherboard. But logically, the Auto setting should force the PCI bus to run at its standard speed of 33.33 MHz for maximum compatibility.

It is recommended that you set the PCI Clock Synchronization Mode BIOS feature to To CPU if you are overclocking the processor FSB up to 12.5%. If you wish to overclock the processor FSB beyond 12.5%, then you should set this BIOS feature to 33.33 MHz.

However, if you do not intend to overclock, this BIOS feature will not have any effect. The PCI bus will remain at 33.33 MHz, no matter what you select.

 

Details of PCI Clock Synchronization Mode

The PCI Clock Synchronization Mode BIOS feature allows you to force the PCI bus to either synchronize itself with the processor FSB (Front Side Bus) speed, or run at the standard clock speed of 33.33 MHz.

When set to To CPU, the PCI bus speed is slaved to the processor’s FSB speed. Any change in FSB speed will result in a similar change in the PCI bus speed. For example, if you increase the processor’s FSB speed by 10%, the PCI bus speed will increase by 10% as well.

When set to 33.33MHz, the PCI bus speed will be locked into its standard clock speed of 33.33 MHz. No matter what the processor’s FSB speed is, the PCI bus will always run at 33.33 MHz.

The Auto option is ambiguous. Without testing, its effect cannot be ascertained since it’s up to the manufacturer what it wishes to implement by default for the motherboard. But logically, the Auto setting should force the PCI bus to run at its standard speed of 33.33 MHz for maximum compatibility.

Synchronizing the PCI bus with the processor FSB allows for greater performance when you are overclocking. Because the PCI bus will be overclocked as you overclock the processor FSB, you will experience better performance from your PCI devices. However, if your PCI device cannot tolerate the overclocked PCI bus, you may experience issues like system crashes or data corruption.

The recommended safe limit for an overclocked PCI bus is 37.5 MHz. This is the speed at which practically all new PCI cards can run at without breaking a sweat. Still, you should test the system thoroughly for stability issues before committing to an overclocked PCI bus speed.

Please note that if you wish to synchronize the PCI bus with the processor FSB and remain within this relatively safe limit, you can only overclock the processor FSB by up to 12.5%. Any higher, your PCI bus will be overclocked beyond 37.5 MHz.

If you wish to overclock the processor FSB further without worrying about your PCI devices, then you should set this BIOS feature to 33.33 MHz. This forces the PCI bus to run at the standard speed of 33.33MHz, irrespective of the processor’s FSB speed.

It is recommended that you set the PCI Clock Synchronization Mode BIOS feature to To CPU if you are overclocking the processor FSB up to 12.5%. If you wish to overclock the processor FSB beyond 12.5%, then you should set this BIOS feature to 33.33 MHz.

However, if you do not intend to overclock, this BIOS feature will not have any effect. The PCI bus will remain at 33.33 MHz, no matter what you select.

 

Recommended Reading

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PCI Chaining from The Tech ARP BIOS Guide

PCI Chaining

Common Options : Enabled, Disabled

 

Quick Review of PCI Chaining

The PCI Chaining BIOS feature is designed to speed up writes from the processor to the PCI bus by allowing write combining to occur at the PCI interface.

When PCI chaining is enabled, up to four quadwords of processor writes to contiguous PCI addresses will be chained together and written to the PCI bus as a single PCI burst write.

When PCI chaining is disabled, each processor write to the PCI bus will be handled as separate non-burst writes of 32-bits.

Needless to say, writing four quadwords of data in a single PCI write is much faster than doing so in four separate non-burstable writes. A single PCI burst write will also reduce the amount of time the processor has to wait while writing to the PCI bus.

Therefore, it is recommended that you enable this BIOS feature for better CPU to PCI write performance.

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Details of PCI Chaining

The PCI Chaining BIOS feature is designed to speed up writes from the processor to the PCI bus by allowing write combining to occur at the PCI interface.

When PCI chaining is enabled, up to four quadwords of processor writes to contiguous PCI addresses will be chained together and written to the PCI bus as a single PCI burst write.

When PCI chaining is disabled, each processor write to the PCI bus will be handled as separate non-burst writes of 32-bits.

Needless to say, writing four quadwords of data in a single PCI write is much faster than doing so in four separate non-burstable writes. A single PCI burst write will also reduce the amount of time the processor has to wait while writing to the PCI bus.

Therefore, it is recommended that you enable this BIOS feature for better CPU to PCI write performance.

 

What Is A Quadword?

In computing, a quadword is a term that means four words, equivalent to 8 bytes or 64-bits.

So a PCI burst write of four quadwords would be 32 bytes, or 256 bits in size. That would be 8X faster than a non-burst write of 4 bytes, or 32 bits in size.

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Byte Merge from The Tech ARP BIOS Guide

Byte Merge

Common Options : Enabled, Disabled

 

Quick Review of Byte Merge

The Byte Merge BIOS feature is similar to the PCI Dynamic Bursting feature.

When enabled, the PCI write buffer accumulates and merges 8-bit and 16-bit writes into 32-bit writes. This increases the efficiency of the PCI bus and improves its bandwidth.

When disabled, the PCI write buffer will not accumulate or merge 8-bit or 16-bit writes. It will just write them to the PCI bus as soon as the bus is free. As such, there may be a loss of PCI bus efficiency when 8-bit or 16-bit data is written to the PCI bus.

Therefore, it is recommended that you enable Byte Merge for better performance.

However, please note that Byte Merge may be incompatible with certain PCI network interface cards (also known as NICs). So, if your NIC won’t work properly, try disabling this feature.

 

Details of Byte Merge

The Byte Merge BIOS feature is similar to the PCI Dynamic Bursting feature.

If you have already read about the CPU to PCI Write Buffer feature, you should know that the chipset has an integrated PCI write buffer which allows the CPU to immediately write up to four words (or 64-bits) of PCI writes to it. This frees up the CPU to work on other tasks while the PCI write buffer writes them to the PCI bus.

Now, the CPU doesn’t always write 32-bit data to the PCI bus. 8-bit and 16-bit writes can also take place. But while the CPU may only write 8-bits of data to the PCI bus, it is still considered as a single PCI transaction. This makes it equivalent to a 16-bit or 32-bit write in terms of PCI bandwidth! This reduces the effective PCI bandwidth, especially if there are many 8-bit or 16-bit CPU-to-PCI writes.

To solve this problem, the write buffer can be programmed to accumulate and merge 8-bit and 16-bit writes into 32-bit writes. The buffer then writes the merged data to the PCI bus. As you can see, merging the smaller 8-bit or 16-bit writes into a few large 32-bit writes reduces the number of PCI transactions required. This increases the efficiency of the PCI bus and improves its bandwidth.

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This is where the Byte Merge BIOS feature comes in. It controls the byte merging capability of the PCI write buffer.

If it is enabled, every write transaction will go straight to the write buffer. They are accumulated until there is enough to be written to the PCI bus in a single burst. This improves the PCI bus’ performance.

If you disable byte merging, all writes will still go to the PCI write buffer (if the CPU to PCI Write Buffer feature has been enabled). But the buffer won’t accumulate and merge the data. The data is written to the PCI bus as soon as the bus becomes free. This reduces PCI bus efficiency, particularly when 8-bit or 16-bit data is written to the PCI bus.

Therefore, it is recommended that you enable Byte Merge for better performance.

However, please note that Byte Merge may be incompatible with certain PCI network interface cards (also known as NICs). Boar-Ral explains :-

I noticed that some PCI cards really despise Byte Merge, in particular the 3Com 3C905 series of NICs. While this may only apply to certain motherboards, in my case, the P3V4X; I feel that this is probably not the case and that it is a rather widespread problem.

Issues I have encountered with Byte Merge enabled, range from Windows 98 SE freezing at the boot screen to my NIC not functioning at all. This issue has been confirmed with others using the same NIC and is what alerted me to the issue in the first place.

Prozactive concurs :-

I wanted to confirm the observation posted by Boar-Ral concerning the “Byte Merge” BIOS setting. After enabling “Byte Merge” and making other recommended BIOS setting changes, I suddenly lost all network I/O from my system. And yes, I happen to be using a 3Com 3C905B-TX NIC (with an Asus A7V motherboard). After a great deal of trial and error troubleshooting, I found that disabling “Byte Merge” lets everything work again.

On the other hand, Cprall discovered that he was able to use the NIC in Windows 98 SE but not in Windows 2000. Check out what he has to say :-

I’ll even third this to say I was recently bitten by the same (A7V motherboard at BIOS 1009 and 3C905B-TX network card). I do have one slight addition to what was seen here. With Byte Merge enabled, I was able to access the network under Windows 98 SE, but not Windows 2000. With Byte Merge disabled, the network card works under both.

So, if your NIC (Network Interface Card) won’t work properly, try disabling Byte Merge. Otherwise, you should enable Byte Merge for better performance.

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PCI Pipelining – The Tech ARP BIOS Guide

PCI Pipelining

Common Options : Enabled, Disabled

 

Quick Review of PCI Pipelining

The PCI Pipelining BIOS feature determines if PCI transactions to the memory subsystem will be pipelined.

If the PCI pipeline feature is enabled, the memory controller allows PCI transactions to be pipelined. This masks the latency of each PCI transaction and improves the efficiency of the PCI bus.

If the PCI pipeline feature is disabled, the memory controller is forced to check for outstanding transactions from other devices to the same block address that each PCI transaction is targeting.

For better PCI performance, the PCI pipeline should be enabled. This allows the latency of the bus to be masked for consecutive transactions.

However, if your system constantly locks up for no apparent reason, try disabling this feature. Disabling PCI Pipelining reduces performance but ensures that data coherency is strictly maintained for maximum reliability.

 

Details of PCI Pipelining

The PCI Pipelining BIOS feature determines if PCI transactions to the memory subsystem will be pipelined.

The pipelining of PCI transactions allows their latencies to be masked (hidden). This greatly improves the efficiency of the PCI bus. However, this is only true for multiple transactions in the same direction. Pipelining won’t help with PCI devices that switch between reads and writes often.

This feature is different from a burst transfer where multiple data transactions are executed consecutively with a single command. In PCI pipelining, different transactions are progressively processed in the pipeline without waiting for the current transaction to finish. Normally, outstanding transactions have to wait for the current one to complete before they are initiated.

If the PCI pipeline feature is enabled, the memory controller allows PCI transactions to be pipelined. This masks the latency of each PCI transaction and improves the efficiency of the PCI bus.

Please note that once the transactions are pipelined, they are flagged as performed, even though they have not actually been completed. As such, data coherency problems may occur when other devices write to the same memory block. This may cause valid data to be overwritten by outdated or expired data, causing problems like data corruption or system lock-ups.

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If the PCI pipeline feature is disabled, the memory controller is forced to check for outstanding transactions from other devices to the same block address that each PCI transaction is targeting.

If there is a match, the PCI transaction is stalled until the outstanding transaction to the same memory block is complete. This essentially forces the memory controller to hold the PCI bus until the PCI transaction is cleared to proceed. It also prevents other PCI transactions from being pipelined. Both factors greatly reduce performance.

For better PCI performance, the PCI pipeline should be enabled. This allows the latency of the bus to be masked for consecutive transactions.

However, if your system constantly locks up for no apparent reason, try disabling this feature. Disabling PCI Pipelining reduces performance but ensures that data coherency is strictly maintained for maximum reliability.

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Delayed Transaction – The BIOS Optimization Guide

Delayed Transaction

Common Options : Enabled, Disabled

 

Quick Review of Delayed Transaction

To meet PCI 2.1 compliance, the PCI maximum target latency rule must be observed. According to this rule, a PCI 2.1-compliant device must service a read request within 16 PCI clock cycles for the initial read and 8 PCI clock cycles for each subsequent read.

If it cannot do so, the PCI bus will terminate the transaction so that other PCI devices can access the bus. But instead of rearbitrating for access (and failing to meet the minimum latency requirement again), the PCI 2.1-compliant device can make use of the PCI Delayed Transaction feature.

With PCI Delayed Transaction enabled, the target device can independently continue the read transaction. So, when the master device successfully gains control of the bus and reissues the read command, the target device will have the data ready for immediate delivery. This ensures that the retried read transaction can be completed within the stipulated latency period.

If the delayed transaction is a write, the master device will rearbitrate for bus access while the target device completes writing the data. When the master device regains control of the bus, it reissues the same write request. This time, the target device just sends the completion status to the master device to complete the transaction.

One advantage of using PCI Delayed Transaction is that it allows other PCI masters to use the bus while the transaction is being carried out on the target device. Otherwise, the bus will be left idling while the target device completes the transaction.

PCI Delayed Transaction also allows write-posted data to remain in the buffer while the PCI bus initiates a non-postable transaction and yet still adhere to the PCI ordering rules. Without PCI Delayed Transaction, all write-posted data will have to be flushed before another PCI transaction can occur.

It is highly recommended that you enable Delayed Transaction for better PCI performance and to meet PCI 2.1 specifications. Disable it only if your PCI cards cannot work properly with this feature enabled or if you are using PCI cards that are not PCI 2.1 compliant.

Please note that while many manuals and even earlier versions of the BIOS Optimization Guide have stated that this is an ISA bus-specific BIOS feature which enables a 32-bit write-posted buffer for faster PCI-to-ISA writes, they are incorrect! This BIOS feature is not ISA bus-specific and it does not control any write-posted buffers. It merely allows write-posting to continue while a non-postable PCI transaction is underway.

 

Details of Delayed Transaction

On the PCI bus, there are many devices that may not meet the PCI target latency rule. Such devices include I/O controllers and bridges (i.e. PCI-to-PCI and PCI-to-ISA bridges). To meet PCI 2.1 compliance, the PCI maximum target latency rule must be observed.

According to this rule, a PCI 2.1-compliant device must service a read request within 16 PCI clock cycles (32 clock cycles for a host bus bridge) for the initial read and 8 PCI clock cycles for each subsequent read. If it cannot do so, the PCI bus will terminate the transaction so that other PCI devices can access the bus. But instead of rearbitrating for access (and failing to meet the minimum latency requirement again), the PCI 2.1-compliant device can make use of the PCI Delayed Transaction feature.

When a master device reads from a target device on the PCI bus but fails to meet the latency requirements; the transaction will be terminated with a Retry command. The master device will then have to rearbitrate for bus access. But if PCI Delayed Transaction had been enabled, the target device can independently continue the read transaction. So, when the master device successfully gains control of the bus and reissues the read command, the target device will have the data ready for immediate delivery. This ensures that the retried read transaction can be completed within the stipulated latency period.

If the delayed transaction is a write, the target device latches on the data and terminates the transaction if it cannot be completed within the target latency period. The master device then rearbitrates for bus access while the target device completes writing the data. When the master device regains control of the bus, it reissues the same write request. This time, instead of returning data (in the case of a read transaction), the target device sends the completion status to the master device to complete the transaction.

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One advantage of using PCI Delayed Transaction is that it allows other PCI masters to use the bus while the transaction is being carried out on the target device. Otherwise, the bus will be left idling while the target device completes the transaction.

PCI Delayed Transaction also allows write-posted data to remain in the buffer while the PCI bus initiates a non-postable transaction and yet still adhere to the PCI ordering rules. The write-posted data will be written to memory while the target device is working on the non-postable transaction and flushed before the transaction is completed on the master device. Without PCI Delayed Transaction, all write-posted data will have to be flushed before another PCI transaction can occur.

As you can see, the PCI Delayed Transaction feature allows for more efficient use of the PCI bus as well as better PCI performance by allowing write-posting to occur concurrently with non-postable transactions. In this BIOS, the Delayed Transaction option allows you to enable or disable the PCI Delayed Transaction feature.

It is highly recommended that you enable Delayed Transaction for better PCI performance and to meet PCI 2.1 specifications. Disable it only if your PCI cards cannot work properly with this feature enabled or if you are using PCI cards that are not PCI 2.1 compliant.

Please note that while many manuals and even earlier versions of the BIOS Optimization Guide have stated that this is an ISA bus-specific BIOS feature which enables a 32-bit write-posted buffer for faster PCI-to-ISA writes, they are incorrect! This BIOS feature is not ISA bus-specific and it does not control any write-posted buffers. It merely allows write-posting to continue while a non-postable PCI transaction is underway.

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PCI Prefetch – The BIOS Optimization Guide

PCI Prefetch

Common Options : Enabled, Disabled

 

Quick Review

The PCI Prefetch feature controls the PCI controller’s prefetch capability.

When enabled, the PCI controller will prefetch data whenever the PCI device reads from the system memory. This speeds up PCI reads as it allows contiguous memory reads by the PCI device to proceed with minimal delay.

Therefore, it is recommended that you enable this feature for better PCI read performance.

 

Details

The PCI Prefetch feature controls the PCI controller’s prefetch capability.

When enabled, the system controller will prefetch eight quadwords (one cache line) of data whenever a PCI device reads from the system memory.

Therefore, it is recommended that you enable this feature for better PCI read performance. Please note that PCI writes to the system memory do not benefit from this feature.

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Here’s how it works.

Whenever the PCI controller reads PCI-requested data from the system memory, it also reads the subsequent cache line of data. This is done on the assumption that the PCI device will request for the subsequent cache line.

When the PCI device actually initiates a read command for that cache line, the system controller can immediately send it to the PCI device.

This speeds up PCI reads as the PCI device won’t need to wait for the system controller to read from the system memory. As such, PCI Prefetch allows contiguous memory reads by the PCI device to proceed with minimal delay.

 

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