Tag Archives: Memory architecture

vivo Virtual RAM For V21, V21e, X60 : How Does It Work?

vivo Virtual RAM For V21, V21e, X60 : How Does It Work?

The vivo V21 series and X60 smartphones now support Virtual RAM / Extended RAM technology!

But what exactly is vivo Virtual RAM, and how does it work?

 

vivo Virtual RAM : How Does It Work?

First introduced in the vivo V21 series, vivo Virtual RAM is basically virtual memory that computers have been using for decades.

When our computers begin to run out of memory, it can use some of our HDD / SDD storage as virtual memory.

While storage speeds are many times slower than RAM speed, this is better than running out of memory, which would cause the app to stop working, or worse, crash the operating system.

vivo Virtual RAM uses the same concept – it utilises 3 GB of the smartphone’s internal storage as virtual memory.

This effectively gives the operating system and apps more memory to use. If your vivo smartphone has 8 GB of RAM, then Virtual RAM expands that to 11 GB.

To improve performance, vivo also borrowed the PC virtual memory technique of swapping out inactive apps into the extended RAM space, so active apps have access to the much faster RAM.

The Virtual RAM technology was introduced in the V21 series, and will soon be added to their flagship X60 smartphone.

 

vivo Virtual RAM : How Useful Is It?

That really depends on how you use your smartphone.

If you only use a few apps at the same time, you will probably never run out of memory.

vivo smartphones now come with a lot of memory – 8 GB, and even games like PUBG Mobile and Asphalt 9 use less than 1.2 GB of RAM!

But if you use many apps simultaneously, or switch between them often, this could help prevent slow loading.

According to vivo, turning on Virtual RAM on an 8 GB smartphone will allow you to cache up to 20 background apps simultaneously.

 

Recommended Reading

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RW Queue Bypass from The Tech ARP BIOS Guide

RW Queue Bypass

Common Options : Auto, 2X, 4X, 8X, 16X

 

Quick Review of RW Queue Bypass

The RW Queue Bypass BIOS setting determines how many times the arbiter is allowed to bypass the oldest memory access request in the DCI’s read/write queue.

Once this limit is reached, the arbiter is overriden and the oldest memory access request serviced instead.

As this feature greatly improves memory performance, most BIOSes will not include a Disabled setting.

Instead, you are allowed to adjust the number of times the arbiter is allowed to bypass the oldest memory access request in the queue.

A high bypass limit will give the arbiter more flexibility in scheduling memory accesses so that it can maximise the number of hits on open memory pages.

This improves the performance of the memory subsystem. However, this comes at the expense of memory access requests that get delayed. Such delays can be a problem for time-sensitive applications.

It is generally recommended that you set the RW Queue Bypass BIOS feature to the maximum value of 16X, which would give the memory controller’s read-write queue arbiter maximum flexibility in scheduling memory access requests.

However, if you face stability issues, especially with time-sensitive applications, reduce the value step-by-step until the problem resolves.

The Auto option, if available, usually sets the bypass limit to the maximum – 16X.

 

Details of RW Queue Bypass

The R/W Queue Bypass BIOS option is similar to the DCQ Bypass Maximum BIOS option – they both decide the limits on which an arbiter can intelligently reschedule memory accesses to improve performance.

The difference between the two is that DCQ Bypass Maximum does this at the memory controller level, while R/W Queue Bypass does it at the Device Control Interface (DCI) level.

To improve performance, the arbiter can reschedule transactions in the DCI read / write queue.

By allowing some transactions to bypass other transactions in the queue, the arbiter can maximize the number of hits on open memory pages.

This improves the overall memory performance but at the expense of some memory accesses which have to be delayed.

The RW Queue Bypass BIOS setting determines how many times the arbiter is allowed to bypass the oldest memory access request in the DCI’s read/write queue.

Once this limit is reached, the arbiter is overriden and the oldest memory access request serviced instead.

As this feature greatly improves memory performance, most BIOSes will not include a Disabled setting.

Instead, you are allowed to adjust the number of times the arbiter is allowed to bypass the oldest memory access request in the queue.

A high bypass limit will give the arbiter more flexibility in scheduling memory accesses so that it can maximise the number of hits on open memory pages.

This improves the performance of the memory subsystem. However, this comes at the expense of memory access requests that get delayed. Such delays can be a problem for time-sensitive applications.

It is generally recommended that you set this BIOS feature to the maximum value of 16X, which would give the memory controller’s read-write queue arbiter maximum flexibility in scheduling memory access requests.

However, if you face stability issues, especially with time-sensitive applications, reduce the value step-by-step until the problem resolves.

The Auto option, if available, usually sets the bypass limit to the maximum – 16X.

Recommended Reading

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Asynclat (Asynchronous Latency) – The Tech ARP BIOS Guide

Asynclat

Common Options : 0 to 15 ns

 

Quick Review of Asynclat

Asynclat is an AMD processor-specific BIOS feature. It controls the amount of asynchronous latency, which depends on the time it takes for data to travel from the processor to the furthest DIMM on the motherboard and back. For your reference, AMD has a few conservative suggestions on setting the Asynclat BIOS feature.

Memory Type

Number Of
DIMM Slots

Memory Clock

200 MHz

166 MHz

133 MHz

100 MHz

Registered

8

8 ns

8 ns

9 ns

9 ns

Unbuffered

4

8 ns

8 ns

8 ns

8 ns

3 or 4

7 ns

7 ns

7 ns

7 ns

1 or 2

6 ns

6 ns

6 ns

6 ns

Do note that in this case, the distance of the furthest DIMM slot is considered analogous to the number of DIMM slots. The greater number of DIMM slots available on the motherboard, the further the final slot is from the memory controller.

Also, these values are rough and conservative recommendations that assume that the furthest DIMM slot is occupied by a module. If your motherboard has four slots and you choose to populate only the first two slots, you could use a shorter asynchronous latency.

Generally, it is recommended that you stick with the asynchronous latency recommended by AMD (see table above) or your memory module’s manufacturer. You can, of course, adjust the amount of asynchronous latency according to the situation. For example, if you are overclocking the memory modules, or if you populate the first two slots of the four available DIMM slots; you can get away with a lower asynchronous latency.

 

Details of Asynclat

Asynclat is an AMD processor-specific BIOS feature. It controls the amount of asynchronous latency, which depends on the time it takes for data to travel from the processor to the furthest DIMM on the motherboard and back.

The asynchronous latency is designed to account for variances in the trace length to the furthest DIMM on the motherboard, as well as the type of DIMM, number of chips in that DIMM and the memory bus frequency. For your reference, AMD has a few conservative suggestions on setting the Asynclat BIOS feature.

Memory Type

Number Of
DIMM Slots

Memory Clock

200 MHz

166 MHz

133 MHz

100 MHz

Registered

8

8 ns

8 ns

9 ns

9 ns

Unbuffered

4

8 ns

8 ns

8 ns

8 ns

3 or 4

7 ns

7 ns

7 ns

7 ns

1 or 2

6 ns

6 ns

6 ns

6 ns

Do note that in this case, the distance of the furthest DIMM slot is considered analogous to the number of DIMM slots. The greater number of DIMM slots available on the motherboard, the further the final slot is from the memory controller.

Also, these values are rough and conservative recommendations that assume that the furthest DIMM slot is occupied by a module. If your motherboard has four slots and you choose to populate only the first two slots, you could use a shorter asynchronous latency.

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Naturally, the shorter the latency, the better the performance. However, if the latency is too short, it will not allow enough time for data to be returned from the furthest DIMM on the motherboard. This results in data corruption and system instability.

The optimal asynchronous latency varies from system to system. It depends on the motherboard design, where you install your DIMMs, the type of DIMM used and the memory bus speed selected. The only way to find the optimal asychronous latency is trial and error, by starting with a high value and working your way down.

Generally, it is recommended that you stick with the asynchronous latency recommended by AMD (see table above) or your memory module’s manufacturer. You can, of course, adjust the amount of asynchronous latency according to the situation. For example, if you are overclocking the memory modules, or if you populate the first two slots of the four available DIMM slots; you can get away with a lower asynchronous latency.

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AMD Vega Memory Architecture Q&A With Jeffrey Cheng

At the AMD Computex 2017 Press Conference, AMD President & CEO Dr. Lisa Su announced that AMD will launch the Radeon Vega Frontier Edition on 27 June 2017, and the Radeon RX Vega graphics cards at the end of July 2017. We figured this is a great time to revisit the new AMD Vega memory architecture.

Now, who better to tell us all about it than AMD Senior Fellow Jeffrey Cheng, who built the AMD Vega memory architecture? Check out this exclusive Q&A session from the AMD Tech Summit in Sonoma!

Updated @ 2017-06-11 : We clarified the difference between the AMD Vega’s 64-bit flat address space, and the 512 TB addressable memory. We also added new key points, and time stamps for the key points.

Originally posted @ 2017-02-04

Don’t forget to also check out the following AMD Vega-related articles :

 

The AMD Vega Memory Architecture

Jeffrey Cheng is an AMD Senior Fellow in the area of memory architecture. The AMD Vega memory architecture refers to how the AMD Vega GPU manages memory utilisation and handles large datasets. It does not deal with the AMD Vega memory hardware design, which includes the High Bandwidth Cache and HBM2 technology.

 

AMD Vega Memory Architecture Q&A Summary

Here are the key takeaway points from the Q&A session with Jeffrey Cheng :

  • Large amounts of DRAM can be used to handle big datasets, but this is not the best solution because DRAM is costly and consumes lots of power (see 2:54).
  • AMD chose to design a heterogenous memory architecture to support various memory technologies like HBM2 and even non-volatile memory (e.g. Radeon Solid State Graphics) (see 4:40 and 8:13).[adrotate group=”2″]
  • At any given moment, the amount of data processed by the GPU is limited, so it doesn’t make sense to store a large dataset in DRAM. It would be better to cache the data required by the GPU on very fast memory (e.g. HBM2), and intelligently move them according to the GPU’s requirements (see 5:40).
  • The AMD Vega’s heterogenous memory architecture allows for easy integration of future memory technologies like storage-class memory (flash memory that can be accessed in bytes, instead of blocks) (see 8:13).
  • The AMD Vega has a 64-bit flat address space for its shaders (see 12:0812:36 and 18:21), but like NVIDIA, AMD is (very likely) limiting the addressable memory to 49-bits, giving it 512 TB of addressable memory.
  • AMD Vega has full access to the CPU’s 48-bit address space, with additional bits beyond that used to handle its own internal memory, storage and registers (see 12:16). This ties back to the High Bandwidth Cache Controller and heterogenous memory architecture, which allows the use of different memory and storage types.

  • Game developers currently try to manage data and memory usage, often extremely conservatively to support graphics cards with limited amounts of graphics memory (see 16:29).
  • With the introduction of AMD Vega, AMD wants game developers to leave data and memory management to the GPU. Its High Bandwidth Cache Controller and heterogenous memory system will automatically handle it for them (see 17:19).
  • The memory architectural advantages of AMD Vega will initially have little impact on gaming performance (due to the current conservative approach of game developers). This will change when developers hand over data and memory management to the GPU. (see 24:42).[adrotate group=”2″]
  • The improved memory architecture in AMD Vega will mainly benefit AI applications (e.g. deep machine learning) with their large datasets (see 24:52).

Don’t forget to also check out the following AMD Vega-related articles :

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Memory Hole At 15M-16M – The BIOS Optimization Guide

Memory Hole At 15M-16M

Common Options : Enabled, Disabled

 

Quick Review

Certain ISA cards require exclusive access to the 1 MB block of memory, from the 15th to the 16th megabyte, to work properly. The Memory Hole At 15M-16M BIOS feature allows you to reserve that 1 MB block of memory for such cards to use.

If you enable this feature, 1 MB of memory (the 15th MB) will be reserved exclusively for the ISA card’s use. This effectively reduces the total amount of memory available to the operating system by 1 MB.

Please note that in certain motherboards, enabling this feature may actually render all memory above the 15th MB unavailable to the operating system!

If you disable this feature, the 15th MB of RAM will not be reserved for the ISA card’s use. The full range of memory is therefore available for the operating system to use. However, if your ISA card requires the use of that memory area, it may then fail to work.

Since ISA cards are a thing of the past, it is highly recommended that you disable this feature. Even if you have an ISA card that you absolutely have to use, you may not actually need to enable this feature.

Most ISA cards do not need exclusive access to this memory area. Make sure that your ISA card requires this memory area before enabling this feature. You should use this BIOS feature only in a last-ditch attempt to get a stubborn ISA card to work.

 

Details

Certain ISA cards require exclusive access to the 1 MB block of memory, from the 15th to the 16th megabyte, to work properly. The Memory Hole At 15M-16M BIOS feature allows you to reserve that 1 MB block of memory for such cards to use.

If you enable this feature, 1 MB of memory (the 15th MB) will be reserved exclusively for the ISA card’s use. This effectively reduces the total amount of memory available to the operating system by 1 MB. Therefore, if you have 256 MB of memory, the usable amount of memory will be reduced to 255 MB.

Please note that in certain motherboards, enabling this feature may actually render all memory above the 15th MB unavailable to the operating system! In such cases, you will end up with only 14 MB of usable memory, irrespective of how much memory your system actually has.

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If you disable this feature, the 15th MB of RAM will not be reserved for the ISA card’s use. The full range of memory is therefore available for the operating system to use. However, if your ISA card requires the use of that memory area, it may then fail to work.

Since ISA cards are a thing of the past, it is highly recommended that you disable this feature. Even if you have an ISA card that you absolutely have to use, you may not actually need to enable this feature.

Most ISA cards do not need exclusive access to this memory area. Make sure that your ISA card requires this memory area before enabling this feature. You should use this BIOS feature only in a last-ditch attempt to get a stubborn ISA card to work.

 

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