Tag Archives: Intel Pentium 4

Compatible FPU OPCODE - The BIOS Optimization Guide

Compatible FPU OPCODE – The BIOS Optimization Guide

Compatible FPU OPCODE - The BIOS Optimization Guide

Compatible FPU OPCODE

Common Options : Enabled, Disabled

 

Quick Review of Compatible FPU OPCODE

The Compatible FPU OPCODE BIOS feature determines how Pentium 4 and Xeon processors handle FOP codes using the FOP (final opcode) register.

When enabled, the Pentium 4 and Xeon will engage the FOP code compatibility mode, which stores the FOP of the last non-transparent instruction in the FOP register.

When disabled, the Pentium 4 and Xeon will turn off the FOP code compatibility mode and store only the FOP of the last non-transparent floating point instruction that had an unmasked exception. This allows for better FPU performance.

Therefore, it is recommended that you disable this feature for better FPU performance unless your software requires this feature to recover from FPU exceptions.

 

Details of Compatible FPU OPCODE

In Intel IA-32 (P6 family, Pentium 4, etc…) processors, the x87 FPU stores the opcode of the last executed non-control instruction (also known as the fopcode or FOP code) in an 11-bit register. This provides state information for exception handlers.

Since the first 5 bits of the first opcode byte are the same for all FPU opcodes, only the last 3 bits of the first opcode byte are stored in the register. The second opcode byte provides the remaining 8-bits of data.

Courtesy of Intel Corporation

In previous implementations, the final opcode (or FOP) to be stored in the FOP register is always the FOP of the last non-transparent floating point instruction executed before a FSAVE or FSTENV or FXSAVE instruction.

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However, to improve FPU performance, the Pentium 4 and Xeon processors will only store the FOP of the last non-transparent floating point instruction that had an unmasked exception. For backward compatibility, the Pentium 4 and Xeon processors allow programmable control of the FOP register. This is where the Compatible FPU OPCODE BIOS feature comes in.

When enabled, the processor will revert to the FOP code compatibility mode and store the last non-transparent floating point instruction in the 11-bit FOP register. Intel recommends that this feature should only be enabled if the software was designed to use the fopcode to analyze program performance or to restart the program after an exception has been handled.

When disabled, the processor will turn off the FOP code compatibility mode and store only the FOP of the last non-transparent floating point instruction that had an unmasked exception. This allows for better FPU performance.

It is recommended that you disable this feature. This allows for better FPU performance although some older programs may require you to enable this feature to allow recovery from FPU exceptions.

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CPU Hyper-Threading – The BIOS Optimization Guide

CPU Hyper-Threading

Common Options : Enabled, Disabled

 

Quick Review

This BIOS feature controls the functionality of the Intel Hyper-Threading Technology.

The Intel Hyper-Threading Technology allows a single processor to execute two or more separate threads concurrently. When it is enabled, multi-threaded software applications can execute their threads in parallel, thereby improving their performance.

The Intel Hyper-Threading Technology is only supported by certain Intel processors, from the Intel Pentium 4 onwards. Please note that for it to work, you should have the following :

  • an Intel processor that supports Hyper-Threading
  • a motherboard with a chipset and BIOS that support Hyper-Threading
  • an operating system which supports Hyper-Threading (Microsoft Windows XP or Linux 2.4.x, or better)

Since it behaves like two separate processors with their own APICs, you should also enable APIC Function in the BIOS, which is required for multi-processing.

It is highly recommended that you enable CPU Hyper-Threading for improved processor performance.

 

Details

The Intel Hyper-Threading Technology is an extension to the IA-32 architecture which allows a single processor to execute two or more separate threads concurrently. When it is enabled, multi-threaded software applications can execute their threads in parallel, thereby improving the processor’s performance.

The current implementation involves two logical processors sharing the processor’s execution engine and its bus interface. Each logical processor, though, will come with its own APIC. The other features of the processor are either shared or duplicated in each logical processor.

Here is a list of the features duplicated in each logical processor :-

  • General registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP and EBP)
  • Segment registers (CS, DS, SS, ES, FS and GS)
  • EFLAGS and EIP registers
  • x87 FPU registers (ST0 to ST7, status word, control word, tag word, data operand pointer and instruction pointer)
  • MMX registers (MM0 to MM7)
  • XMM registers (XMM0 to XMM7)
  • MXCSR register
  • Control registers (CR0, CR2, CR3, CR4)
  • System table pointer registers (GDTR, LDTR, IDTR, task register)
  • Debug registers (DR0, DR1, DR2, DR3, DR6, DR7)
  • Debug control MSR (IA32_DEBUGCTL)
  • Machine check global status MSR (IA32_MCG_STATUS)
  • Machine check capability MSR (IA32_MCG_CAP)
  • Thermal clock modulation and ACPI power management control MSRs
  • Time stamp counter MSRs
  • Most of the other MSR registers including Page Attribute Table (PAT)
  • Local APIC registers
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Here are the features shared by the two logical processors :-

  • IA32_MISC_ENABLE MSR
  • Memory type range registers (MTRRs)

And the following are features that can be duplicated or shared according to requirements :-

  • Machine check architecture (MCA) MSRs
  • Performance monitoring control and counter MSRs

The Intel Hyper-Threading Technology is only supported by certain Intel processors, from the Intel Pentium 4 onwards. Please note that for it to work, you should have the following :

  • an Intel processor that supports Hyper-Threading
  • a motherboard with a chipset and BIOS that support Hyper-Threading
  • an operating system which supports Hyper-Threading (Microsoft Windows XP or Linux 2.4.x, or better)

Since it behaves like two separate processors with their own APICs, you should also enable APIC Function in the BIOS, which is required for multi-processing.

It is highly recommended that you enable CPU Hyper-Threading for improved processor performance.

 

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CPU Hardware Prefetch – The BIOS Optimization Guide

CPU Hardware Prefetch

Common Options : Enabled, Disabled

 

Quick Review

The processor has a hardware prefetcher that automatically analyzes its requirements and prefetches data and instructions from the memory into the Level 2 cache that are likely to be required in the near future. This reduces the latency associated with memory reads.

When enabled, the processor’s hardware prefetcher will be enabled and allowed to automatically prefetch data and code for the processor.

When disabled, the processor’s hardware prefetcher will be disabled.

If you are using a C1 stepping (or older) of the Intel Pentium 4 or Intel Pentium 4 Xeon processor, it is recommended that you enable this BIOS feature so that the hardware prefetcher is enabled for maximum performance.

But if you are using an older version of the Intel Pentium 4 or Intel Pentium 4 Xeon processor, then you should disable the CPU Hardware Prefetch BIOS feature to circumvent the O37 bug which causes data corruption when the hardware prefetcher is operational.

 

Details

CPU Hardware Prefetch is a BIOS feature specific to processors based on the Intel NetBurst microarchitecture (e.g. Intel Pentium 4 and Intel Pentium 4 Xeon).

These processors have a hardware prefetcher that automatically analyzes the processor’s requirements and prefetches data and instructions from the memory into the Level 2 cache that are likely to be required in the near future. This reduces the latency associated with memory reads.

When it works, the hardware prefetcher does a great job of keeping the processor loaded with code and data. However, it doesn’t always work right.

Prior to the C1 stepping of the Intel Pentium 4 and Intel Pentium 4 Xeon, these processors shipped with a bug that causes data corruption when the hardware prefetcher was enabled. According to Intel, Errata O37 causes the processor to “use stale data from the cache while the Hardware Prefetcher is enabled“.

Unfortunately, the only solution for the affected processors is to disable the hardware prefetcher. This is where the CPU Hardware Prefetch BIOS feature comes in.

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When enabled, the processor’s hardware prefetcher will be enabled and allowed to automatically prefetch data and code for the processor.

When disabled, the processor’s hardware prefetcher will be disabled.

If you are using a C1 stepping (or older) of the Intel Pentium 4 or Intel Pentium 4 Xeon processor, it is recommended that you enable this BIOS feature so that the hardware prefetcher is enabled for maximum performance.

But if you are using an older version of the Intel Pentium 4 or Intel Pentium 4 Xeon processor, then you should disable this BIOS feature to circumvent the O37 bug which causes data corruption when the hardware prefetcher is operational.

 

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Differential Current – The BIOS Optimization Guide

Differential Current

Common Options : 4x Iref, 5x Iref, 6x Iref, 7x Iref

 

Quick Review

The Differential Current BIOS feature allows you to change the amount of differential current produced by the clock driver pairs, effectively changing the voltage swing of the system clocks.

When set to 4x Iref, the current difference is four times that of Iref, the reference current source.

When set to 5x Iref, the current difference is five times that of Iref, the reference current source.

When set to 6x Iref, the current difference is six times that of Iref, the reference current source.

When set to 7x Iref, the current difference is seven times that of Iref, the reference current source.

By default, the Differential Current BIOS feature is set to 4x Iref. Unfortunately, it is not known what that translate to in voltage. Not even the Iref value is known. However, the higher the differential current, the greater the voltage swing.

As a higher voltage swing improves integrity of the clock signals and overall system stability, it is recommended that you set this BIOS feature to 7x Iref for a higher differential current. However, please note that this will increase the amount of EMI (Electromagnetic Interference) produced by the motherboard.

 

Details

In the Intel Pentium 4 platform, the voltage swing used by the system clocks is not derived from a common voltage source. Instead, it uses Iref or the reference current source to drive pairs of clock drivers that produce differential currents. These differential currents are used to set the voltage swing of the various system clocks.

This new clocking method reduces the effect of noise on the voltage swing of the system clocks. This results in better timing margins which can translate into tighter, faster timings or better stability.

The Differential Current BIOS feature allows you to change the amount of differential current produced by the clock driver pairs, effectively changing the voltage swing of the system clocks.

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When set to 4x Iref, the current difference is four times that of Iref, the reference current source.

When set to 5x Iref, the current difference is five times that of Iref, the reference current source.

When set to 6x Iref, the current difference is six times that of Iref, the reference current source.

When set to 7x Iref, the current difference is seven times that of Iref, the reference current source.

By default, the Differential Current BIOS feature is set to 4x Iref. Unfortunately, it is not known what that translate to in voltage. Not even the Iref value is known.

However, the higher the differential current, the greater the voltage swing. In other words, 4x Iref produces the lowest voltage swing while 7x Iref produces the highest voltage swing.

As a higher voltage swing improves integrity of the clock signals and overall system stability, it is recommended that you set this BIOS feature to 7x Iref for a higher differential current. However, please note that this will increase the amount of EMI (Electromagnetic Interference) produced by the motherboard.

 

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