Tag Archives: BIOS Optimisation Guide

Hard Disk Pre-Delay from The Tech ARP BIOS Guide!

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Hard Disk Pre-Delay

Common Options : Disabled, 3 Seconds, 6 Seconds, 9 Seconds, 12 Seconds, 15 Seconds, 21 Seconds, 30 Seconds

 

Hard Disk Pre-Delay : A Quick Review

The Hard Disk Pre-Delay BIOS feature allows you to force the BIOS to delay the initialisation of your hard disk drives for up to 30 seconds. The delay allows your IDE devices more time to spin up before the BIOS initializes them.

If you do not use old IDE drives and the BIOS has no problem initializing your IDE devices, it is recommended that you disable this BIOS feature for the shortest possible booting time. Most IDE devices will have no problem spinning up in time for initialisation.

But if one or more of your IDE devices fail to initialize during the boot up process, start with a delay of 3 Seconds. If that doesn’t help, gradually increase the delay until all your IDE devices initialize properly during the boot up process.

 

Hard Disk Pre-Delay : The Full Details

Regardless of its shortcomings, the IDE standard is remarkably backward-compatible. Every upgrade of the standard was designed to be fully compatible with older IDE devices. So, you can actually use the old 40 MB hard disk drive that came with your ancient 386 system in your much newer Athlon XP system!

However, even backward compatibility cannot account for the slower motors used in the older IDE drives. Crucially, motherboards are capable of booting up much faster these days, initialising IDE devices much earlier.

Unfortunately, this also means that some older IDE drives will not be able to spin up in time to be initialized! When this happens, the BIOS will not be able to detect that IDE drive and the drive will not be accessible even though it is actually running just fine.

This is where the Hard Disk Pre-Delay BIOS feature comes in. It allows you to force the BIOS to delay the initialisation of your hard disk drives for up to 30 seconds. The delay allows your IDE devices more time to spin up before the BIOS initializes them.

If you do not use old IDE drives and the BIOS has no problem initializing your IDE devices, it is recommended that you disable this BIOS feature for the shortest possible booting time. Most IDE devices will have no problem spinning up in time for initialization.

But if one or more of your IDE devices fail to initialize during the boot up process, start with a delay of 3 Seconds. If that doesn’t help, gradually increase the delay until all your IDE devices initialize properly during the boot up process.

 

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IDE Bus Master Support from The Tech ARP BIOS Guide!

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IDE Bus Master Support

Common Options : Enabled, Disabled

 

Quick Review of IDE Bus Master Support

The IDE Bus Master Support BIOS feature is a misnomer since it doesn’t actually control the bus mastering ability of the onboard IDE controller.

It is actually a toggle for the built-in driver that allows the onboard IDE controller to perform DMA (Direct Memory Access) transfers.

When this BIOS feature is enabled, the BIOS loads up the 16-bit busmastering driver for the onboard IDE controller. This allows the IDE controller to transfer data via DMA, resulting in greatly improved transfer rates and lower CPU utilization in real mode DOS and during the loading of other operating systems.

When this BIOS feature is disabled, the BIOS will not load up the 16-bit busmastering driver for the onboard IDE controller. The IDE controller will then transfer data via PIO.

Therefore, it is recommended that you enable IDE Bus Master Support. This greatly improves the IDE transfer rate and reduces the CPU utilization during the booting process or when you are using real mode DOS. Users of DOS-based disk utilities like Norton Ghost can expect to benefit a lot from this feature.

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Details of IDE Bus Master Support

The IDE Bus Master Support BIOS feature is a misnomer since it doesn’t actually control the bus mastering ability of the onboard IDE controller.

It is actually a toggle for the built-in driver that allows the onboard IDE controller to perform DMA (Direct Memory Access) transfers.

DMA transfer modes allow IDE devices to transfer large amounts of data from the hard disk to the system memory and vice versa with minimal processor intervention.

It differs from the older and processor-intensive PIO transfer modes by offloading the task of data transfer from the processor to the chipset.

Previously, this feature is only available after an operating system that supports DMA transfers (via the appropriate device driver) is loaded up.

But now, many BIOS come with a built-in 16-bit driver that allows DMA transfers. This allows the onboard IDE controller to perform DMA transfers even before the operating system is loaded up!

When this BIOS feature is enabled, the BIOS loads up the 16-bit busmastering driver for the onboard IDE controller. This allows the IDE controller to transfer data via DMA, resulting in greatly improved transfer rates and lower CPU utilization in real mode DOS and during the loading of other operating systems.

When this BIOS feature is disabled, the BIOS will not load up the 16-bit busmastering driver for the onboard IDE controller. The IDE controller will then transfer data via PIO.

Therefore, it is recommended that you enable IDE Bus Master Support. This greatly improves the IDE transfer rate and reduces the CPU utilization during the booting process or when you are using real mode DOS. Users of DOS-based disk utilities like Norton Ghost can expect to benefit a lot from this feature.

Please note that since current operating systems (i.e. Windows XP) load up their own 32-bit busmastering driver, this feature has no effect once such an operating system loads up. Still, it is recommended that you enable this feature to improve performance prior to the loading of the operating system’s own driver.

 

Recommended Reading

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Multi-Sector Transfers from The Tech ARP BIOS Guide

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Multi-Sector Transfers

Common Options : Disabled, 2 Sectors, 4 Sectors, 8 Sectors, 16 Sectors, 32 Sectors, Maximum

 

Quick Review of Multi-Sector Transfers

The Multi-Sector Transfers BIOS feature speeds up hard disk drive access by transferring multiple sectors of data per interrupt instead of using the usual single-sector transfer mode. This mode of transferring data is known as block transfers.

There are a few available options, from Disabled and a few different multiple sectors option to Maximum.

The Disabled option forces your IDE controller to transfer only a single sector (512 bytes) per interrupt. Needless to say, this will significantly degrade performance.

The selection of 2 Sectors to 32 Sectors allows you to manually select the number of sectors that the IDE controller is allowed to transfer per interrupt.

The Maximum option allows your IDE controller to transfer as many sectors per interrupt as the hard disk is able to support.

Since all current hard disk drives support block transfers, there is usually no reason why IDE HDD Block Mode should be disabled.

Therefore, you should disable IDE HDD Block Mode only if you actually face the possibility of data corruption (with an unpatched version of Windows NT 4.0). Otherwise, it is highly recommended that you select the Maximum option for significantly better hard disk performance!

The manual selection of 2 to 32 sectors is useful if you notice data corruption with the Maximum option. It allows you to scale back the multi-sector transfer feature to correct the problem without losing too much performance.

 

Details of Multi-Sector Transfers

The Multi-Sector Transfers BIOS feature speeds up hard disk drive access by transferring multiple sectors of data per interrupt instead of using the usual single-sector transfer mode. This mode of transferring data is known as block transfers.

There are a few available options, from Disabled and a few different multiple sectors option to Maximum.

The Disabled option forces your IDE controller to transfer only a single sector (512 bytes) per interrupt. Needless to say, this will significantly degrade performance.

The selection of 2 Sectors to 32 Sectors allows you to manually select the number of sectors that the IDE controller is allowed to transfer per interrupt.

The Maximum option allows your IDE controller to transfer as many sectors per interrupt as the hard disk is able to support.

Since all current hard disk drives support block transfers, there is usually no reason why IDE HDD Block Mode should be disabled.

However, if you are running on Windows NT 4.0, you might need to disable this BIOS feature because Windows NT 4.0 has a problem with block transfers. According to Chris Bope, Windows NT does not support IDE HDD Block Mode and enabling this feature can cause data to be corrupted.

Ryu Connor confirmed this by sending me a link to a Microsoft article (Enhanced IDE operation under Windows NT 4.0). According to this article, IDE HDD Block Mode and 32-bit Disk Access have been found to cause data corruption in some cases. Therefore, Microsoft recommends that Windows NT 4.0 users disable IDE HDD Block Mode.

Lord Mike asked ‘someone in the know‘ about this matter and he was told that the data corruption issue was taken very seriously at Microsoft and that it had been corrected through the Windows NT 4.0 Service Pack 2. Although he could not get an official statement from Microsoft, it is probably safe enough to enable IDE HDD Block Mode on a Windows NT 4.0 system, just as long as it has been upgraded with Service Pack 2.

Therefore, you should disable IDE HDD Block Mode only if you actually face the possibility of data corruption (with an unpatched version of Windows NT 4.0). Otherwise, it is highly recommended that you select the Maximum option for significantly better hard disk performance!

The manual selection of 2 to 32 sectors is useful if you notice data corruption with the Maximum option. It allows you to scale back the multi-sector transfer feature to correct the problem without losing too much performance.

 

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PCI Chaining from The Tech ARP BIOS Guide

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PCI Chaining

Common Options : Enabled, Disabled

 

Quick Review of PCI Chaining

The PCI Chaining BIOS feature is designed to speed up writes from the processor to the PCI bus by allowing write combining to occur at the PCI interface.

When PCI chaining is enabled, up to four quadwords of processor writes to contiguous PCI addresses will be chained together and written to the PCI bus as a single PCI burst write.

When PCI chaining is disabled, each processor write to the PCI bus will be handled as separate non-burst writes of 32-bits.

Needless to say, writing four quadwords of data in a single PCI write is much faster than doing so in four separate non-burstable writes. A single PCI burst write will also reduce the amount of time the processor has to wait while writing to the PCI bus.

Therefore, it is recommended that you enable this BIOS feature for better CPU to PCI write performance.

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Details of PCI Chaining

The PCI Chaining BIOS feature is designed to speed up writes from the processor to the PCI bus by allowing write combining to occur at the PCI interface.

When PCI chaining is enabled, up to four quadwords of processor writes to contiguous PCI addresses will be chained together and written to the PCI bus as a single PCI burst write.

When PCI chaining is disabled, each processor write to the PCI bus will be handled as separate non-burst writes of 32-bits.

Needless to say, writing four quadwords of data in a single PCI write is much faster than doing so in four separate non-burstable writes. A single PCI burst write will also reduce the amount of time the processor has to wait while writing to the PCI bus.

Therefore, it is recommended that you enable this BIOS feature for better CPU to PCI write performance.

 

What Is A Quadword?

In computing, a quadword is a term that means four words, equivalent to 8 bytes or 64-bits.

So a PCI burst write of four quadwords would be 32 bytes, or 256 bits in size. That would be 8X faster than a non-burst write of 4 bytes, or 32 bits in size.

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CPU L2 Cache ECC Checking from The Tech ARP BIOS Guide

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CPU L2 Cache ECC Checking

Common Options : Enabled, Disabled

 

Quick Review of CPU L2 Cache ECC Checking

The CPU L2 Cache ECC Checking BIOS feature enables or disables the L2 (Level 2 or Secondary) cache’s ECC (Error Checking and Correction) capability, if available.

Enabling this feature is recommended because it will detect and correct single-bit errors in data stored in the L2 cache. As most data reads are satisfied by the L2 cache, the L2 cache’s ECC function should catch and correct almost all single-bit errors in the memory subsystem.

It will also detect double-bit errors although it cannot correct them. But this isn’t such a big deal since double-bit errors are extremely rare. For all practical purposes, the ECC check should be able to catch virtually all data errors. This is especially useful at overclocked speeds when errors are most likely to creep in.

So, for most intents and purposes, I recommend that you enable this feature for greater system stability and reliability.

Please note that the presence of this feature in the BIOS does not necessarily mean that your processor’s L2 cache actually supports ECC checking. Many processors do not ship with ECC-capable L2 cache. In such cases, you can still enable this feature in the BIOS, but it will have no effect.

 

Details of CPU L2 Cache ECC Checking

The CPU L2 Cache ECC Checking BIOS feature enables or disables the L2 (Level 2 or Secondary) cache’s ECC (Error Checking and Correction) capability, if available.

Enabling this feature is recommended because it will detect and correct single-bit errors in data stored in the L2 cache. As most data reads are satisfied by the L2 cache, the L2 cache’s ECC function should catch and correct almost all single-bit errors in the memory subsystem.

It will also detect double-bit errors although it cannot correct them. But this isn’t such a big deal since double-bit errors are extremely rare. For all practical purposes, the ECC check should be able to catch virtually all data errors. This is especially useful at overclocked speeds when errors are most likely to creep in.

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There are those who advocate disabling ECC checking because it reduces performance. True, ECC checking doesn’t come free. You can expect some performance degradation with ECC checking enabled. However, unlike ECC checking of DRAM modules, the performance degradation associated with L2 cache ECC checking is comparatively small.

Balance that against the increased stability and reliability achieved via L2 cache ECC checking and the minimal reduction in performance seems rather cheap, doesn’t it? Of course, if you don’t do any serious work with your system and want a little speed boost for your games, disable CPU L2 Cache ECC Checking by all means.

But if you are overclocking your processor, ECC checking may enable you to overclock higher than was originally possible. This is because any single-bit errors that occur as a result of overclocking will be corrected by the L2 cache’s ECC function. So, for most intents and purposes, I recommend that you enable this feature for greater system stability and reliability.

Please note that the presence of this feature in the BIOS does not necessarily mean that your processor’s L2 cache actually supports ECC checking. Many processors do not ship with ECC-capable L2 cache. In such cases, you can still enable this feature in the BIOS, but it will have no effect.

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