Tag Archives: AMD Tech Summit

AMD Vega Memory Architecture Q&A With Jeffrey Cheng

AMD Vega Memory Architecture Q&A With Jeffrey Cheng

At the AMD Computex 2017 Press Conference, AMD President & CEO Dr. Lisa Su announced that AMD will launch the Radeon Vega Frontier Edition on 27 June 2017, and the Radeon RX Vega graphics cards at the end of July 2017. We figured this is a great time to revisit the new AMD Vega memory architecture.

Now, who better to tell us all about it than AMD Senior Fellow Jeffrey Cheng, who built the AMD Vega memory architecture? Check out this exclusive Q&A session from the AMD Tech Summit in Sonoma!

Updated @ 2017-06-11 : We clarified the difference between the AMD Vega’s 64-bit flat address space, and the 512 TB addressable memory. We also added new key points, and time stamps for the key points.

Originally posted @ 2017-02-04

Don’t forget to also check out the following AMD Vega-related articles :

 

The AMD Vega Memory Architecture

Jeffrey Cheng is an AMD Senior Fellow in the area of memory architecture. The AMD Vega memory architecture refers to how the AMD Vega GPU manages memory utilisation and handles large datasets. It does not deal with the AMD Vega memory hardware design, which includes the High Bandwidth Cache and HBM2 technology.

 

AMD Vega Memory Architecture Q&A Summary

Here are the key takeaway points from the Q&A session with Jeffrey Cheng :

  • Large amounts of DRAM can be used to handle big datasets, but this is not the best solution because DRAM is costly and consumes lots of power (see 2:54).
  • AMD chose to design a heterogenous memory architecture to support various memory technologies like HBM2 and even non-volatile memory (e.g. Radeon Solid State Graphics) (see 4:40 and 8:13).[adrotate group=”2″]
  • At any given moment, the amount of data processed by the GPU is limited, so it doesn’t make sense to store a large dataset in DRAM. It would be better to cache the data required by the GPU on very fast memory (e.g. HBM2), and intelligently move them according to the GPU’s requirements (see 5:40).
  • The AMD Vega’s heterogenous memory architecture allows for easy integration of future memory technologies like storage-class memory (flash memory that can be accessed in bytes, instead of blocks) (see 8:13).
  • The AMD Vega has a 64-bit flat address space for its shaders (see 12:0812:36 and 18:21), but like NVIDIA, AMD is (very likely) limiting the addressable memory to 49-bits, giving it 512 TB of addressable memory.
  • AMD Vega has full access to the CPU’s 48-bit address space, with additional bits beyond that used to handle its own internal memory, storage and registers (see 12:16). This ties back to the High Bandwidth Cache Controller and heterogenous memory architecture, which allows the use of different memory and storage types.

  • Game developers currently try to manage data and memory usage, often extremely conservatively to support graphics cards with limited amounts of graphics memory (see 16:29).
  • With the introduction of AMD Vega, AMD wants game developers to leave data and memory management to the GPU. Its High Bandwidth Cache Controller and heterogenous memory system will automatically handle it for them (see 17:19).
  • The memory architectural advantages of AMD Vega will initially have little impact on gaming performance (due to the current conservative approach of game developers). This will change when developers hand over data and memory management to the GPU. (see 24:42).[adrotate group=”2″]
  • The improved memory architecture in AMD Vega will mainly benefit AI applications (e.g. deep machine learning) with their large datasets (see 24:52).

Don’t forget to also check out the following AMD Vega-related articles :

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The AMD FreeSync 2 Q&A With David Glen & Syed Hussain

AMD is going to expand their royalty-free FreeSync technology this year with the introduction of Radeon FreeSync 2. If you have already read our FreeSync 2 tech briefing earlier, you know that FreeSync 2 promises to offer HDR gaming with minimal input lag.

While waiting for AMD to finalise Radeon FreeSync 2 and its certification program for their partners, let’s share with you our Q&A session with the two key AMD engineers in charge of the Radeon FreeSync 2 project – David Glen and Syed Athar Hussain.

 

The AMD FreeSync 2 Q&A With David Glen & Syed Hussain

AMD Senior Fellow Architect David Glen and AMD Display Domain Fellow Syed Athar Hussain are  the main guys heading the Radeon FreeSync 2 project. In this informal Q&A session held on the last day of the AMD Tech Summit in Sonoma, they give us more details on FreeSync 2.

An interesting point in this Q&A session is how the wide colour gamuts that many monitors support these days are not being utilised at all. Hope you enjoy it. Sorry about the noise though. There seemed to be some interference from nearby devices.

For those who prefer a summary of what they discussed and answered, here are the key takeaways :
  • Radeon FreeSync 2 is an AMD proprietary standard, but they will eventually push for it to be an open standard.[adrotate banner=”4″]
  • Radeon FreeSync 2 is not an AMD Vega-specific technology. It is a backward-compatible technology.
  • All GPUs that support FreeSync will support FreeSync 2, via a driver update.
  • FreeSync 2 will not be part of the Radeon Software Crimson ReLive Edition. It will only be introduced in the following Radeon Software edition.
  • FreeSync 2 will support the FP16 and 2-10-10-10 colour buffer formats, that current AMD Radeon Software drivers already support.
  • The AMD FreeSync 2 API will allow developers to quickly add FreeSync 2 capability to their games and game engines.
  • Games that do not integrate the AMD FreeSync 2 API, or use game engines that support it, will not be able to automatically switch to HDR mode, or use the FreeSync 2 transport.

  • The AMD FreeSync 2 monitor certification program will include stringent requirements for low latency (for native and scaled resolutions) and colour space, with an AMD lab to ensure that those monitors meet the minimum requirements.
  • FreeSync 2 will not deliver the colour space of HDR10 or Dolby Vision, but it’s designed to greatly expand the colour space with minimal input lag.

  • The input lag as specified in the AMD FreeSync 2 specifications is defined as the lag from the display flip to when photons are emitted.
  • There will be two-way communications between the monitor and the graphics card. The monitor’s capabilities are conveyed to the graphics subsystem, and the graphics subsystem will instruct the monitor to go into its “native operation mode” to make full use of its native colour space.
  • FreeSync 2 will support both active (two-dimensional) backlights and global illuminating backlights.

MORE : You can read more about Radeon FreeSync 2 in our article – The Radeon FreeSync 2 HDR Gaming Tech Report.

 

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The Complete AMD Radeon Instinct Tech Briefing Rev. 3.0

The AMD Tech Summit held in Sonoma, California from December 7-9, 2016 was not only very exclusive, it was highly secretive. The first major announcement we have been allowed to reveal is the new AMD Radeon Instinct heterogenous computing platform.

In this article, you will hear from AMD what the Radeon Instinct platform is all about. As usual, we have a ton of videos from the event, so it will be as if you were there with us. Enjoy! 🙂

Originally published @ 2016-12-12

Updated @ 2017-01-11 : Two of the videos were edited to comply with the NDA. Now that the NDA on AMD Vega has been lifted, we replaced the two videos with their full, unedited versions. We also made other changes, including adding links to the other AMD Tech Summit articles.

Updated @ 2017-01-20 : Replaced an incorrect slide, and a video featuring that slide. Made other small updates to the article.

 

The AMD Radeon Instinct Platform Summarised

For those who want the quick low-down on AMD Radeon Instinct, here are the key takeaway points :

  • The AMD Radeon Instinct platform is made up of two components – hardware and software.
  • The hardware components are the AMD Radeon Instinct accelerators built around the current Polaris and the upcoming Vega GPUs.
  • The software component is the AMD Radeon Open Compute (ROCm) platform, which includes the new MIOpen open-source deep learning library.
  • The first three Radeon Instinct accelerator cards are the MI6, MI8 and MI25 Vega with NCU.
  • The AMD Radeon Instinct MI6 is a passively-cooled inference accelerator with 5.7 TFLOPS of FP16 processing power, 224 GB/s of memory bandwidth, and a TDP of <150 W. It will come with 16 GB of GDDR5 memory.
  • The AMD Radeon Instinct MI8 is a small form-factor (SFF) accelerator with 8.2 TFLOPS of processing power, 512 GB/s of memory bandwidth, and a TDP of <175 W. It will come with 4 GB of HBM memory.
  • The AMD Radeon Instinct MI25 Vega with NCU is a passively-cooled training accelerator with 25 TFLOPS of processing power, support for 2X packed math, a High Bandwidth Cache and Controller, and a TDP of <300 W.
  • The Radeon Instinct accelerators will all be built exclusively by AMD.
  • The Radeon Instinct accelerators will all support MxGPU SRIOV hardware virtualisation.
  • The Radeon Instinct accelerators are all passively cooled.
  • The Radeon Instinct accelerators will all have large BAR (Base Address Register) support for multiple GPUs.
  • The upcoming AMD Zen “Naples” server platform is designed to supported multiple Radeon Instinct accelerators through a high-speed network fabric.
  • The ROCm platform is not only open source, it will support a multitude of standards in addition to MIOpen.
  • The MIOpen deep learning library is open source, and will be available in Q1 2017.
  • The MIOpen deep learning library is optimised for Radeon Instinct, allowing for 3X better performance in machine learning.
  • AMD Radeon Instinct accelerators will be significantly faster than NVIDIA Titan X GPUs based on the Maxwell and Pascal architectures.

In the subsequent pages, we will give you the full low-down on the Radeon Instinct platform, with the following presentations by AMD :

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We also prepared the complete video and slides of the Radeon Instinct tech briefing for your perusal :

Next Page > Heterogenous Computing, The Radeon Instinct Accelerators, MIOpen, Performance

 

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Why Is Heterogenous Computing Important?

Dr. Lisa Su, kicked things off with an inside look at her two-year long journey as AMD President and CEO. Then she revealed why Heterogenous Computing is an important part of AMD’s future going forward. She also mentioned the success of the recently-released Radeon Software Crimson ReLive Edition.

 

Here Are The New AMD Radeon Instinct Accelerators!

Next, Raja Koduri, Senior Vice President and Chief Architect of the Radeon Technologies Group, officially revealed the new AMD Radeon Instinct accelerators.

 

The MIOpen Deep Learning Library For Radeon Instinct

MIOpen is a new deep learning library optimised for Radeon Instinct. It is open source and will become part of the Radeon Open Compute (ROCm) platform. It will be available in Q1 2017.

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The Performance Advantage Of Radeon Instinct & MIOpen

MIOpen is optimised for Radeon Instinct, offering 3X better performance in machine learning. It allows the Radeon Instinct accelerators to be significantly faster than NVIDIA Titan X GPUs based on the Maxwell and Pascal architectures.

Next Page > Radeon Instinct MI25 & MI8 Demos, Zen “Naples” Platform, The First Servers, ROCm Discussion

 

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The Radeon Instinct MI25 Training Demonstration

Raja Koduri roped in Ben Sander, Senior Fellow at AMD, to show off the Radeon Instinct MI25 running a training demo.

 

The Radeon Instinct MI8 Visual Inference Demonstration

The visual inference demo is probably much easier to grasp, as it is visual in nature. AMD used the Radeon Instinct MI8 in this example.

 

The Radeon Instinct On The Zen “Naples” Platform

The upcoming AMD Zen “Naples” server platform is designed to supported multiple AMD Radeon Instinct accelerators through a high-speed network fabric.

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The First Radeon Instinct Servers

This is not a vapourware launch. Raja Koduri revealed the first slew of Radeon Instinct servers that will hit the market in H1 2017.

 

The Radeon Open Compute (ROCm) Platform Discussion

To illustrate the importance of heterogenous computing on Radeon Instinct, Greg Stoner (ROCm Senior Director at AMD), hosted a panel of AMD partners and early adopters in using the Radeon Open Compute (ROCm) platform.

Next Page > Closing Remarks On Radeon Instinct, The Complete Radeon Instinct Tech Briefing Video & Slides

 

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Closing Remarks On Radeon Instinct

Finally, Raja Koduri concluded the launch of the Radeon Instinct Initiative with some closing remarks on the recent Radeon Software Crimson ReLive Edition.

 

The Complete AMD Radeon Instinct Tech Briefing

This is the complete AMD Radeon Instinct tech briefing. Our earlier video was edited to comply with the AMD Vega NDA (which has now expired).

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The Complete AMD Radeon Instinct Tech Briefing Slides

Here are the Radeon Instinct presentation slides for your perusal.

 

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Watch AMD Vega Run DOOM On Vulkan!

AMD recently revealed architectural details of the upcoming Vega GPU, but many people were disappointed that AMD is not ready to launch it yet. Will it matter how fantastic AMD Vega is on paper if it’s nowhere close to reality? The good news is AMD appears to be close to the final silicon.

In fact, at the AMD Tech Summit in Sonoma, we were shown an AMD Vega prototype running DOOM on Vulkan. Billy Khan from id Software also came to vouch for the performance and stability of the latest Vega silicon.

 

Watch AMD Vega Run DOOM On Vulkan!

AMD showed off this Vega prototype running DOOM at the 4K resolution of 3840 x 2160, using the Ultra Quality preset. DOOM was running with the Vulkan upgrade, of course, which allows for asynchronous compute. The video shows the Vega prototype deliver frame rates of 60-70 fps, with an average of 65 fps.

We tried to take a closer look inside the chassis to catch a look of the AMD Vega graphics card, but it appears to be well-shielded from our view. All we can say is that the card appears to be rather quiet… at least it was not audible in the hubbub of the room.

 

id Software On AMD Vega And Vulkan

Earlier that day, Billy Khan (Lead Project Programmer of id Tech 6 and DOOM) spoke about AMD Vega and Vulkan. Here are the key takeaway points :

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  • Vulkan brings “close to the metal” coding to the PC
  • This allows for closer development of console and PC games
  • Micro-optimisations are now very easy to port from consoles to PC
  • They have been running DOOM at 4K on super high quality at over 70 fps on an early (few weeks old) AMD Vega silicon

We came away with the feeling that Billy was very impressed with the performance and stability of the Vega GPU. Hopefully, this will assuage the frustrations of AMD fans who are eager to see the AMD Vega to take on the NVIDIA Pascal…

 

The AMD Vega Launch Date

Right now, AMD will not reveal how close they are to the final silicon. Only that they aim to launch Vega in the first half of 2017.

For more information on AMD Vega, take a look at our AMD Vega GPU Architecture Tech Report.

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The First AMD Naples + Radeon Instinct Reference Design Revealed!

We had earlier revealed the upcoming AMD Ryzen desktop processor, and the AMD Radeon Instinct compute accelerators. But that was not all they revealed at the AMD Tech Summit held in Sonoma last month. AMD also showcased the world’s first AMD Naples and Radeon Instinct reference design!

This is a compact 2U (19″) server with two AMD Naples processors, and two Radeon Instinct accelerators. Check it out!

 

What Is AMD Naples?

Formerly known as Summit Ridge, the AMD Ryzen is an octa-core desktop processor that promises to match, if not beat, the Intel Core i7-6900K in both performance and power consumption. Like Ryzen, the AMD Naples processor is based on the AMD Zen microarchitecture. But instead of having just 8 cores, AMD Naples is a server-class processor that boasts 32 cores!

Like Intel Xeon processors, the AMD Naples processor can process two threads per core. So the 32-core AMD Naples processor can handle up to 64 threads simultaneously. It will also reportedly feature a massive 512 MB L3 cache.

Compared that to the top-of-the-line Intel Xeon E7-8890 v4 processor that only has 24 cores and handles up to 48 threads simultaneously, and only has a 60 MB L3 cache.

If the AMD Naples processor delivers the same performance and power consumption we saw with AMD Ryzen, then it should deliver at least 33% better compute performance than the Intel Xeon E7-8890 v4 processor, and blow it out of the water in memory performance. Now that will be a killer server CPU.

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Compute Boost With Radeon Instinct

If the potentially superior AMD Naples compute performance does not impress you, the reference design also showcased the new AMD Radeon Instinct accelerators. Their 2U server reference design featured what appears to be two AMD Radeon Instinct MI8 SFF accelerators.

The Radeon Instinct MI8 is a passively-cooled accelerator that requires only 175 W of power. Each MI8 accelerator delivers 8.2 TFLOPS of FP16 compute performance with 512 GB/s of memory bandwidth. So two of them will offer over 16 TFLOPs of FP16 compute performance in this 2U server.

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The AMD Vega GPU Architecture Tech Report

We can reveal the fourth and, arguably, the biggest news out of the AMD Tech Summit that was held in Sonoma, California from December 7-9, 2016 – details of the new AMD Vega GPU architecture!

In this article, we will reveal to you, the details of not just the Vega NCU (Next-Gen Compute Unit) and the HBM2 memory it uses, but also its spanking new High-Bandwidth Cache Controller. On top of that, we will delve into the new geometry pipeline and pixel engine!

As usual, we will offer you a summary of the key points, and greater details in the subsequent pages. Finally, we will give you the presentation slides and when we get it, the presentation video from the AMD Tech Summit in Sonoma.

 

The 4 Major Features In AMD Vega

As AMD’s next-generation GPU architecture, Vega will come with these 4 major features that will help it to leapfrog ahead of competing graphics architectures.

We will summarise the key points below. But for more details, click on the links above.

 

High-Bandwidth Cache

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  • High-Bandwidth Cache = HBM2 memory + High-Bandwidth Cache Controller (HBCC)
  • HBM2 memory technology offers :
    • 2X bandwidth per pin over HBM
    • 5X power efficiency over GDDR5
    • 8X capacity / stack
    • Over 50% smaller footprint compared to GDDR5
  • The High-Bandwidth Cache Controller offers :
    • Access to 512 TB virtual address space
    • Adaptive, fine-grained data movement
  • AMD showcased the performance of the High-Bandwidth Cache using a real-time render of Joe Macri’s living room on Radeon ProRender with 700+ GB of data

 

New Programmable Geometry Pipeline

  • The new AMD Vega geometry pipeline has over 2X peak throughput per clock
  • There is a new primitive shader that allows primitives to be discarded at a high rate
  • A new Intelligent Workgroup Distributor allows for improved load balancing

 

Next-Generation Compute Unit (NCU)

  • The AMD Vega NCU has configurable precision, allowing it to process :
    • 512 8-bits ops per clock, or
    • 256 16-bit ops per clock, or
    • 128 32-bit ops per clock
  • It is also optimised for higher clock speeds and higher IPC
  • It boasts a larger instruction buffer, and higher clock speeds

 

Next-Generation Pixel Engine

  • The AMD Vega pixel engine has a new Draw Stream Binning Rasteriser
  • The new rasteriser is designed to improve performance while saving power
  • The on-chip bin cache allows the rasteriser to only “fetch once”
  • The rasteriser also “shade once” by culling pixels invisible in the final scene
  • The render back-ends are now clients of the L2 cache, which improves deferred shading performance

 

I Want To Know More!

If you would like to know more about the four main improvements in the AMD Vega GPU architecture, please click on the following links, or just go on to the next page.

Next Page > High-Bandwidth Cache, HBM2 Memory, Cache Controller, Why Is It Called A Cache?

 

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High-Bandwidth Cache

AMD Vega will use HBM2 memory, as well as a new High-Bandwidth Cache Controller (HBCC). Together, they are known as the High Bandwidth Cache.

AMD showcased the performance of the High-Bandwidth Cache using a real-time render of Joe Macri’s living room on Radeon ProRender with 700+ GB of data. Although no frame rate was visible, the real-time render appeared to be very smooth.

 

The HBM2 Memory

HBM2 offers twice the transfer rate per pin (up to 2 GT/s), over its the first-generation HBM memory. This allows it to achieve up to 256 GB/s memory bandwidth per package.

In both HBM and HBM2, up to 8 memory dies can be stacked in a package. But moving to HBM2 allows for twice the memory density – up to 8 GB per package is now possible.

 

The High-Bandwidth Cache Controller

The second component of the High Bandwidth Cache is the new High-Bandwidth Cache Controller (HBCC). It creates a homogenous memory system for the AMD Vega GPU, with up to 512 TB of addressable memory.

It also allows for the adaptive, fine-grained movement of data between the AMD Vega GPU and the system memory, the NVRAM and the network storage (as part of Infinity Fabric).

 

Why Is It Called A Cache?

AMD calls the combination of the HBM2 memory and the High-Bandwidth Cache Controller the “High-Bandwidth Cache“. Techies may wonder why AMD chose to call it “cache”, instead of “memory”. After all, HBM2 memory is a type of fast graphics memory.

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The answer lies in the AMD Vega’s heterogenous memory system. All memory in the system, whether it’s the HBM2 memory or shared memory from the computer’s SDRAM, is seen as a contiguous memory space. A big block of memory, irrespective of how fast they are.

That may be great for memory addressing, but may cause frequently-used data to be placed in slower memory. To avoid such an occurrence, the High-Bandwidth Cache Controller uses the HBM2 memory like a fast cache. This allows it to keep the most frequently-used data in the fastest memory available – the HBM2 memory.

Hence, the HBM2 memory functions like a cache in AMD Vega, and that is why AMD called the combination the High-Bandwidth Cache.

Next Page > New AMD Vega Geometry Pipeline, Compute Unit & Pixel Engine

 

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The New Programmable Geometry Pipeline

The AMD Vega features a new programmable geometry pipeline. It boasts over twice the peak throughput per clock, compared to the previous-generation geometry pipeline. This is achieved through two new improvements – primitive shaders and the Intelligent Workgroup Distributor.

The primitive shader stage is a completely new addition. It allows for primitives to be discarded at a much higher rate. The Intelligent Workgroup Distributor, on the other hand, improves the load balancing of work going to the large number of pipelines.

 

The Next-Generation Compute Unit (NCU)

The AMD Vega NCU is optimised for higher clock speeds, and higher IPC. It boasts a larger instruction buffer, and naturally – high clock speeds. But what’s unique is its flexible, configurable precision. This allows it to process, not just 64-bit and 32-bit operations, but also 16-bit and 8-bit operations. For example, the AMD Vega NCU can process :

  • 512 8-bits ops per clock, or
  • 256 16-bit ops per clock, or
  • 128 32-bit ops per clock

The Vega NCU does not “waste” computing power by only allowing one operation per clock. If it is a smaller-sized operation, it can be combined to maximise performance. This allows it to boost the performance of “packed math” applications.

This is how the new Radeon Instinct MI25 Vega accelerators deliver 25 teraflops of FP16 compute performance. You can read more about Radeon Instinct in the following articles :

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The Next-Generation Pixel Engine

The AMD Vega pixel engine has a new Draw Stream Binning Rasteriser. It is designed to improve performance while saving power. The on-chip bin cache allows it to only “fetch once“, and it culls pixels invisible to the final scene so it can also “shade once“.

In previous GPU architectures, the pixel and texture memory accesses are non-coherent. That means the same data required by both pixel and texture shaders are not “visible”, and have to be fetched and flushed independently. This reduces efficiency and wastes cache bandwidth.

In the AMD Vega GPU, the homogenous memory system allows for coherent memory accesses. In addition, the render back-ends are now clients of the L2 cache. This allows data to remain in the L1 and L2 caches, and not get flushed and refetched over and over again.

Next Page > The Complete AMD Vega GPU Architecture Slides

 

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The Complete AMD Vega GPU Architecture Slides

Here is the full set of official AMD slides on the AMD Vega GPU architecture for your perusal :

We hope to get our hands on the two AMD video presentations on the Vega GPU at the AMD Tech Summit. If we do get them, we will post them here. So check back later! 🙂

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