AMD Zen 3 Tech Report : What’s New, What’s Unchanged?

Take a look at what’s new in the AMD Zen 3 microarchitecture, and what they borrowed from the last-gen Zen 2 microarchitecture!


AMD Zen 3 Architecture

Codename Vermeer, Zen 3 is the next evolution of the AMD Zen architecture.

While it obviously borrowed considerably from the existing Zen 2 architecture, AMD says it is a ground-up redesign that with major performance and functionality improvements in every area of the core.

These architectural changes allow Zen 3-based processors, like the Ryzen 5000 series, to deliver a 19% improvement in instructions per clock (IPC).

Front-End Enhancements

  • Faster fetching, especially for branchy and large-footprint code
  • L1 branch target buffer doubled in size to 1024 entries for better prediction latency
  • Improved branch predictor bandwidth
  • Faster recovery from misprediction
  • “No bubble” prediction capabilities to make back-to-back predictions more quickly and better handle branchy code
  • Faster sequencing of op-cache fetches
  • Finer granularity in switching of op-cache pipes

Execution Engines

  • Reduce latency and enlarge structures to extract higher instruction-level parallelism (ILP)
  • New dedicated branch and st-data pickers for integer, now at 10 issues per cycle (+3 vs. Zen 2)
  • Larger integer window at +32 vs. Zen 2
  • Reduced latency for select float and int operations
  • Floating point has increased bandwidth by +2 for a total of 6-wide dispatch and issue
  • Floating point FMAC is now 1 cycle faster

Load Store

  • Larger structures and better prefetching to support the enhanced execution engine bandwidth
  • Overall higher bandwidth to feed the appetite of the larger/faster execution resources
  • Higher load bandwidth vs. Zen 2 by +1
  • Higher store bandwidth vs. Zen 2 by +1
  • More flexibility in load/store operations
  • Improved memory dependence detection
  • +4 table walkers in the TLB

SOC Architecture

  • Reduce dependency on main memory accesses, reduce core-to-core latency, reduce core-to-cache latency.
  • Unify all cores in a CCD into a single unified complex consisting of 4, 6, or 8 contiguous cores
  • Unify all L3 cache in a CCD into a single contiguous element of up to 32 MB
  • Rearchitect core/cache communication into a ring system


AMD Zen 3 SoC Design

In addition to micro architectural improvements, Zen 3 (Vermeer) also features SoC design changes.

In Zen 2, each CCD (Compute Die) is made up of two CCX (core complexes), each with a 16 MB L3 cache.

Zen 3 uses a unified complex, in which each CCD now contains a single CCX with a unified 32 MB L3 cache.

This unified CCD design completely eliminates CCX-to-CCX communication, greatly improving core-to-core latency.

On the other hand, AMD reused the chiplet design, with one or two CCDs (fabricated on 7 nm) paired with a 12 nm IOD (I/O Die).

Reads from CCD to IO are still 2X write, to conserve die area and transistor budget. And it uses the same IOD from Matisse (Zen 2).


AMD Zen 3 Transistor Count + Die Size

The new Zen 3 CCD has 4.15 billion transistors, with a die size of 80.7 mm². That’s up from the 3.8 billion transistors and a die size of 74 mm² for the Zen 2 CCD.

The Matisse-era IOD remains the same – 2.09 billion transistors, with a die size of 125 mm².

They will both be manufactured using the same 7 nm TSMC process for CCD, and 12 nm Global Foundries process for IOD.

Core Die Zen 3 Zen 2
Process 7 nm TSMC
Transistors 4.15 billion 3.8 billion
Die Size 80.7 mm² 74 mm²
I/O Die Zen 3 Zen 2
Process 12 nm GoFlo
Transistors 2.09 billion
Die Size 125 mm²


AMD Zen 3 Precision Boost : No Change

Precision Boost 2 in Zen 3 remains the same as that of Zen 2, just with higher frequencies to “play with”.

It is an opportunistic boost algorithm that drives the loaded cores to the highest possible frequency, until it hits any one of these limits :

  • socket power
  • VRM thermal limit
  • VRM current limit
  • maximum clock speed

Precision Boost 2 will dynamically analyse and boost or dither the core clock speeds every 1 ms using the Infinity Fabric command and control functions.

In this example of the new Ryzen 9 5900X with a base clock of 3.7 GHz and a boost clock of 4.8 GHz, Precision Boost 2 will typically result in frequencies of 4.4 GHz to 4.6 GHz, even with 24 threads running at the same time.


AMD Zen 3 Voltage Range : No Change

Despite the changes in the microarchitecture and SoC design, Zen 3 processors will continue to be engineered with the same voltage range as Zen- and Zen 2-based processors.

The typical voltage range will vary according to usage, but basically, Zen 3 processors, like the Ryzen 5000 series, will support 0.2 V to 1.5 V.


AMD Zen 3 Temperature Range : No Change

AMD Zen 3-based processors will also have the same temperature ranges as Zen- and Zen 2-based processors.

Note : The temperature range below assumes an enclosed chassis, and an air-conditioned room.


AMD Zen 3 Memory Overclocking : No Change

Only the Zen 3 core chiplet die (CCD) is new in the Ryzen 5000 series processors. They continue to use the same IO die (IOD) as the 3rd Gen Ryzen processors.

Therefore, the relationship between Infinity Fabric Clock (fclk), Memory Controller Clock (uclk) and Memory Clock (mclk) remains the same.

For optimal performance, they are synchronous – in a 1:1:1 ratio. But users can choose a 1:1:2 ratio if they have trouble overclocking memory.


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