We can reveal the fourth and, arguably, the biggest news out of the AMD Tech Summit that was held in Sonoma, California from December 7-9, 2016 – details of the new AMD Vega GPU architecture!

In this article, we will reveal to you, the details of not just the Vega NCU (Next-Gen Compute Unit) and the HBM2 memory it uses, but also its spanking new High-Bandwidth Cache Controller. On top of that, we will delve into the new geometry pipeline and pixel engine!

As usual, we will offer you a summary of the key points, and greater details in the subsequent pages. Finally, we will give you the presentation slides and when we get it, the presentation video from the AMD Tech Summit in Sonoma.

 

The 4 Major Features In AMD Vega

As AMD’s next-generation GPU architecture, Vega will come with these 4 major features that will help it to leapfrog ahead of competing graphics architectures.

• High-Bandwidth Cache (HBM2 memory + High-Bandwidth Cache Controller)
• New Programmable Geometry Pipeline, with improved load balancing and new primitive shader
• Next-Generation Compute Unit (NCU), with configurable precision
• Next-Generation Pixel Engine, with a new rasteriser and L2 cache design

We will summarise the key points below. But for more details, click on the links above.

 

High-Bandwidth Cache

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• High-Bandwidth Cache = HBM2 memory + High-Bandwidth Cache Controller (HBCC)
• HBM2 memory technology offers :
  • 2X bandwidth per pin over HBM
  • 5X power efficiency over GDDR5
  • 8X capacity / stack
  • Over 50% smaller footprint compared to GDDR5
• The High-Bandwidth Cache Controller offers :
  • Access to 512 TB virtual address space
  • Adaptive, fine-grained data movement
• AMD showcased the performance of the High-Bandwidth Cache using a real-time render of Joe Macri’s living room on Radeon ProRender with 700+ GB of data

 

New Programmable Geometry Pipeline

• The new AMD Vega geometry pipeline has over 2X peak throughput per clock
• There is a new primitive shader that allows primitives to be discarded at a high rate
• A new Intelligent Workgroup Distributor allows for improved load balancing

 

Next-Generation Compute Unit (NCU)

• The AMD Vega NCU has configurable precision, allowing it to process :
  • 512 8-bits ops per clock, or
  • 256 16-bit ops per clock, or
  • 128 32-bit ops per clock
• It is also optimised for higher clock speeds and higher IPC
• It boasts a larger instruction buffer, and higher clock speeds

 

Next-Generation Pixel Engine

• The AMD Vega pixel engine has a new Draw Stream Binning Rasteriser
• The new rasteriser is designed to improve performance while saving power
• The on-chip bin cache allows the rasteriser to only “fetch once”
• The rasteriser also “shade once” by culling pixels invisible in the final scene
• The render back-ends are now clients of the L2 cache, which improves deferred shading performance

 

I Want To Know More!

If you would like to know more about the four main improvements in the AMD Vega GPU architecture, please click on the following links, or just go on to the next page.

• High-Bandwidth Cache
• New Programmable Geometry Pipeline
• Next-Generation Compute Unit (NCU)
• Next-Generation Pixel Engine
• The Complete Set Of AMD Vega Architecture Slides

Next Page > High-Bandwidth Cache, HBM2 Memory, Cache Controller, Why Is It Called A Cache?

 

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