Write Data In to Read Delay from The Tech ARP BIOS Guide!

Write Data In to Read Delay

Common Options : 1 Cycle, 2 Cycles

Write Data In to Read Delay : A Quick Review

The Write Data In to Read Delay BIOS feature controls the Write Data In to Read Command Delay (tWTR) memory timing.

This constitutes the minimum number of clock cycles that must occur between the last valid write operation and the next read command to the same internal bank of the DDR device.

The 1 Cycle option naturally offers faster switching from writes to reads and consequently better read performance.

The 2 Cycles option reduces read performance but it will improve stability, especially at higher clock speeds. It may also allow the memory chips to run at a higher speed. In other words, increasing this delay may allow you to overclock the memory module higher than is normally possible.

It is recommended that you select the 1 Cycle option for better memory read performance if you are using DDR266 or DDR333 memory modules. You can also try using the 1 Cycle option with DDR400 memory modules. But if you face stability issues, revert to the default setting of 2 Cycles.

Write Data In to Read Delay : The Full Details

The Write Data In to Read Delay BIOS feature controls the Write Data In to Read Command Delay (tWTR) memory timing.

This constitutes the minimum number of clock cycles that must occur between the last valid write operation and the next read command to the same internal bank of the DDR device.

Please note that this is only applicable for read commands that follow a write operation. Consecutive read operations or writes that follow reads are not affected.

If a 1 Cycle delay is selected, every read command that follows a write operation will be delayed one clock cycle before it is issued.

The 1 Cycle option naturally offers faster switching from writes to reads and consequently better read performance.

If a 2 Cycles delay is selected, every read command that follows a write operation will be delayed two clock cycles before it is issued.

By default, this BIOS feature is set to 2 Cycles. This meets JEDEC’s specification of 2 clock cycles for write-to-read command delay in DDR400 memory modules. DDR266 and DDR333 memory modules require a write-to-read command delay of only 1 clock cycle.

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Write Data In to Read Delay from The Tech ARP BIOS Guide!