SDRAM Trrd Timing Value from The Tech ARP BIOS Guide!

SDRAM Trrd Timing Value

Common Options : 2 cycles, 3 cycles

SDRAM Trrd Timing Value : A Quick Review

The SDRAM Trrd Timing Value BIOS feature specifies the minimum amount of time between successive ACTIVATE commands to the same DDR device.

The shorter the delay, the faster the next bank can be activated for read or write operations. However, because row activation requires a lot of current, using a short delay may cause excessive current surges.

For desktop PCs, a delay of 2 cycles is recommended as current surges aren’t really important. The performance benefit of using the shorter 2 cycles delay is of far greater interest.

The shorter delay means every back-to-back bank activation will take one clock cycle less to perform. This improves the DDR device’s read and write performance.

Switch to 3 cycles only when there are stability problems with the 2 cycles setting.

SDRAM Trrd Timing Value : The Details

The Bank-to-Bank Delay or tRRD is a DDR timing parameter which specifies the minimum amount of time between successive ACTIVATE commands to the same DDR device, even to different internal banks.

Because this timing parameter is DDR device-specific, it may differ from one DDR device to another. DDR DRAM manufacturers typically specify the tRRD parameter based on the row ACTIVATE activity to limit current surges within the device.

If you let the BIOS automatically configure your DRAM parameters, it will retrieve the manufacturer-set tRRD value from the SPD (Serial Presence Detect) chip. However, you may want to manually set the tRRD parameter to suit your requirements.

For desktop PCs, a delay of 2 cycles is recommended as current surges aren’t really important.

This is because the desktop PC essentially has an unlimited power supply and even the most basic desktop cooling solution is sufficient to dispel any extra thermal load that the current surges may impose.

The performance benefit of using the shorter 2 cycles delay is of far greater interest. The shorter delay means every back-to-back bank activation will take one clock cycle less to perform. This improves the DDR device’s read and write performance.

Note that the shorter delay of 2 cycles works with most DDR DIMMs, even at 133 MHz (266 MHz DDR). However, DDR DIMMs running beyond 133 MHz (266 MHz DDR) may need to introduce a delay of 3 cycles between each successive bank activation.

Select 2 cycles whenever possible for optimal DDR DRAM performance.

Switch to 3 cycles only when there are stability problems with the 2 cycles setting.

In mobile devices like laptops however, it would be advisable to use the longer delay of 3 cycles.

Doing so limits the current surges that accompany row activations. This reduces the DDR device’s power consumption and thermal output, both of which should be of great interest to the road warrior.

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SDRAM Trrd Timing Value from The Tech ARP BIOS Guide!