SDRAM Cycle Length from The Tech ARP BIOS Guide

SDRAM Cycle Length from The Tech ARP BIOS Guide

SDRAM Cycle Length

Common Options : 2, 3 (SDR memory) or 1.5, 2, 2.5, 3 (DDR memory)

 

Quick Review of SDRAM Cycle Length

The SDRAM Cycle Length BIOS feature is same as the SDRAM CAS Latency Time BIOS feature. It controls the delay (in clock cycles) between the assertion of the CAS signal and the availability of the data from the target memory cell. It also determines the number of clock cycles required for the completion of the first part of a burst transfer. In other words, the lower the CAS latency, the faster memory reads or writes can occur.

Please note that some memory modules may not be able to handle the lower latency and may lose data. Therefore, while it is recommended that you reduce the SDRAM CAS Latency Time to 2 or 2.5 clock cycles for better memory performance, you should increase it if your system becomes unstable.

Interestingly, increasing the CAS latency time will often allow the memory module to run at a higher clock speed. So, if you hit a snag while overclocking your SDRAM modules, try increasing the CAS latency time.

 

Details of SDRAM Cycle Length

Whenever a read command is issued, a memory row is activated using the RAS (Row Address Strobe). Then, to read data from the target memory cell, the appropriate column is activated using the CAS (Column Address Strobe).

Multiple cells can be read from the same active row by applying the appropriate CAS signals. However, there is a short delay after each assertion of the CAS signal before data can be read from the target memory cell. This delay is known as the CAS latency.

The appropriate delay for your memory module is reflected in its rated timings. In JEDEC specifications, it is the first number in the three or four number sequence. For example, if your memory module has the rated timings of 2-3-4-7, its rated CAS latency would be 2 clock cycles.

The SDRAM Cycle Length BIOS feature is same as the SDRAM CAS Latency Time BIOS feature. It controls the delay (in clock cycles) between the assertion of the CAS signal and the availability of the data from the target memory cell. It also determines the number of clock cycles required for the completion of the first part of a burst transfer. In other words, the lower the CAS latency, the faster memory reads or writes can occur.

Because column activation occurs every time a new memory cell is read from, the effect of CAS latency on memory performance is significant, especially with SDR SDRAM. Its effect is less obvious in DDR SDRAM.

Please note that some memory modules may not be able to handle the lower latency and may lose data. Therefore, while it is recommended that you reduce the SDRAM CAS Latency Time to 2 or 2.5 clock cycles for better memory performance, you should increase it if your system becomes unstable.

Interestingly, increasing the CAS latency time will often allow the memory module to run at a higher clock speed. So, if you hit a snag while overclocking your SDRAM modules, try increasing the CAS latency time.

This is particularly true for DDR SDRAM memory since CAS latency has much less effect on performance with such memory, compared to the older SDR memory. The improvement in overclockability with higher CAS latencies cannot be underestimated. If you are interested in overclocking your DDR SDRAM modules, you might want to consider increasing the CAS latency. The huge increase in overclockability far outweighs the minor loss in performance.

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