PCI Timeout

Common Options : Enabled, Disabled

 

Quick Review

To meet PCI 2.1 compliance, the PCI maximum target latency rule must be observed. According to this rule, a PCI 2.1-compliant device must service a read request within 16 PCI clock cycles for the initial read and 8 PCI clock cycles for each subsequent read.

If it cannot do so, the PCI bus will terminate the transaction so that other PCI devices can access the bus. But instead of rearbitrating for access (and failing to meet the minimum latency requirement again), the PCI 2.1-compliant device can make use of the PCI Timeout feature.

With PCI Timeout enabled, the target device can independently continue the read transaction. So, when the master device successfully gains control of the bus and reissues the read command, the target device will have the data ready for immediate delivery. This ensures that the retried read transaction can be completed within the stipulated latency period.

If the delayed transaction is a write, the master device will rearbitrate for bus access while the target device completes writing the data. When the master device regains control of the bus, it reissues the same write request. This time, the target device just sends the completion status to the master device to complete the transaction.

One advantage of using PCI Timeout is that it allows other PCI masters to use the bus while the transaction is being carried out on the target device. Otherwise, the bus will be left idling while the target device completes the transaction.

PCI Timeout also allows write-posted data to remain in the buffer while the PCI bus initiates a non-postable transaction and yet still adhere to the PCI ordering rules. Without PCI Timeout, all write-posted data will have to be flushed before another PCI transaction can occur.

It is highly recommended that you enable PCI Timeout for better PCI performance and to meet PCI 2.1 specifications. Disable it only if your PCI cards cannot work properly with this feature enabled or if you are using PCI cards that are not PCI 2.1 compliant.

 

Details

This is the same as the Delayed Transaction BIOS feature because it refers to the PCI Delayed Transaction feature which is part of the PCI Revision 2.1 specifications.

On the PCI bus, there are many devices that may not meet the PCI target latency rule. Such devices include I/O controllers and bridges (i.e. PCI-to-PCI and PCI-to-ISA bridges). To meet PCI 2.1 compliance, the PCI maximum target latency rule must be observed.

According to this rule, a PCI 2.1-compliant device must service a read request within 16 PCI clock cycles (32 clock cycles for a host bus bridge) for the initial read and 8 PCI clock cycles for each subsequent read. If it cannot do so, the PCI bus will terminate the transaction so that other PCI devices can access the bus. But instead of rearbitrating for access (and failing to meet the minimum latency requirement again), the PCI 2.1-compliant device can make use of the PCI Timeout feature.

When a master device reads from a target device on the PCI bus but fails to meet the latency requirements; the transaction will be terminated with a Retry command. The master device will then have to rearbitrate for bus access. But if PCI Timeout had been enabled, the target device can independently continue the read transaction. So, when the master device successfully gains control of the bus and reissues the read command, the target device will have the data ready for immediate delivery. This ensures that the retried read transaction can be completed within the stipulated latency period.

If the delayed transaction is a write, the target device latches on the data and terminates the transaction if it cannot be completed within the target latency period. The master device then rearbitrates for bus access while the target device completes writing the data. When the master device regains control of the bus, it reissues the same write request. This time, instead of returning data (in the case of a read transaction), the target device sends the completion status to the master device to complete the transaction.

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One advantage of using PCI Timeout is that it allows other PCI masters to use the bus while the transaction is being carried out on the target device. Otherwise, the bus will be left idling while the target device completes the transaction.

PCI Timeout also allows write-posted data to remain in the buffer while the PCI bus initiates a non-postable transaction and yet still adhere to the PCI ordering rules. The write-posted data will be written to memory while the target device is working on the non-postable transaction and flushed before the transaction is completed on the master device. Without PCI Timeout, all write-posted data will have to be flushed before another PCI transaction can occur.

As you can see, the PCI Timeout feature allows for more efficient use of the PCI bus as well as better PCI performance by allowing write-posting to occur concurrently with non-postable transactions. In this BIOS, the PCI 2.1 Compliance option allows you to enable or disable the PCI Timeout feature.

It is highly recommended that you enable PCI Timeout for better PCI performance and to meet PCI 2.1 specifications. Disable it only if your PCI cards cannot work properly with this feature enabled or if you are using PCI cards that are not PCI 2.1 compliant.

 

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