PCI Pipelining – The Tech ARP BIOS Guide

PCI Pipelining - The Tech ARP BIOS Guide

PCI Pipelining

Common Options : Enabled, Disabled

 

Quick Review of PCI Pipelining

The PCI Pipelining BIOS feature determines if PCI transactions to the memory subsystem will be pipelined.

If the PCI pipeline feature is enabled, the memory controller allows PCI transactions to be pipelined. This masks the latency of each PCI transaction and improves the efficiency of the PCI bus.

If the PCI pipeline feature is disabled, the memory controller is forced to check for outstanding transactions from other devices to the same block address that each PCI transaction is targeting.

For better PCI performance, the PCI pipeline should be enabled. This allows the latency of the bus to be masked for consecutive transactions.

However, if your system constantly locks up for no apparent reason, try disabling this feature. Disabling PCI Pipelining reduces performance but ensures that data coherency is strictly maintained for maximum reliability.

 

Details of PCI Pipelining

The PCI Pipelining BIOS feature determines if PCI transactions to the memory subsystem will be pipelined.

The pipelining of PCI transactions allows their latencies to be masked (hidden). This greatly improves the efficiency of the PCI bus. However, this is only true for multiple transactions in the same direction. Pipelining won’t help with PCI devices that switch between reads and writes often.

This feature is different from a burst transfer where multiple data transactions are executed consecutively with a single command. In PCI pipelining, different transactions are progressively processed in the pipeline without waiting for the current transaction to finish. Normally, outstanding transactions have to wait for the current one to complete before they are initiated.

If the PCI pipeline feature is enabled, the memory controller allows PCI transactions to be pipelined. This masks the latency of each PCI transaction and improves the efficiency of the PCI bus.

Please note that once the transactions are pipelined, they are flagged as performed, even though they have not actually been completed. As such, data coherency problems may occur when other devices write to the same memory block. This may cause valid data to be overwritten by outdated or expired data, causing problems like data corruption or system lock-ups.

If the PCI pipeline feature is disabled, the memory controller is forced to check for outstanding transactions from other devices to the same block address that each PCI transaction is targeting.

If there is a match, the PCI transaction is stalled until the outstanding transaction to the same memory block is complete. This essentially forces the memory controller to hold the PCI bus until the PCI transaction is cleared to proceed. It also prevents other PCI transactions from being pipelined. Both factors greatly reduce performance.

For better PCI performance, the PCI pipeline should be enabled. This allows the latency of the bus to be masked for consecutive transactions.

However, if your system constantly locks up for no apparent reason, try disabling this feature. Disabling PCI Pipelining reduces performance but ensures that data coherency is strictly maintained for maximum reliability.

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