PCI-E Reference Clock from The Tech ARP BIOS Guide

PCI-E Reference Clock from The Tech ARP BIOS Guide

PCI-E Reference Clock

Common Options : 100 MHz, adjustable in 1 MHz steps

 

Quick Review of PCI-E Reference Clock

All PCI Express slots use a 100 MHz reference clock to generate its clocking signals. This is where the PCI-E Reference Clock BIOS option comes in. It controls the frequency of the PCI Express reference clock.

By default, the PCI-E Reference Clock is set to 100 MHz. This is the official reference clock speed for the PCI Express interface. Some BIOSes allow you to adjust this reference clock, usually in steps of 1 MHz.

Adjusting the PCI Express reference clock changes its signalling rate and bandwidth. However, because the PCI Express x16 interface already has such high bandwidth, overclocking it would only have a small effect on real world performance.

In motherboards that suffer from the PCI Express x1 bug, adjusting the reference clock speed up or down can potentially “trick” the motherboard to restore the PCI Express slot to its full x16 mode. However, raising the PCI Express reference clock to 120 MHz can cause timing-sensitive PCI Express devices like SATA controllers to fail. Therefore, it is recommended that you do not exceed 115 MHz, should you choose to overclock the PCI Express reference clock.

 

Details of PCI-E Reference Clock

The PCI Express interface is made up of a series of unidirectional, serial point-to-point links. Each PCI Express lane consists of a pair of those links, making it bidirectional. In its slowest form (PCI Express 1.x), each PCI Express lane has a data transfer rate of 250 MB/s in each direction. The newer PCI Express 2.0 doubles the data transfer rate to 500 MB/s per lane.

For high-bandwidth applications, multiple PCI Express lanes are used to greatly increase the data transfer rate. Each PCI Express slot can support a variety of lanes, from just one lane (x1) up to 32 lanes (x32). At the moment though, the “widest” slot available is the PCI Express x16.

In motherboards that support the PCI Express 1.x standard, the x16 slot delivers a maximum bandwidth of 4 GB/s with a signalling rate of 2.5 gigatransfers per second. The new PCI Express 2.0 standard doubles the signalling rate and the x16 slot’s bandwidth to 8 GB/s.

Whether your motherboard supports the PCI Express 1.x standard or the newer PCI Express 2.0 standard, all PCI Express slots use a 100 MHz reference clock to generate its clocking signals. This is where the PCI-E Reference Clock BIOS option comes in. It controls the frequency of the PCI Express reference clock.

By default, the PCI-E Reference Clock is set to 100 MHz. This is the official reference clock speed for the PCI Express interface. Some BIOSes allow you to adjust this reference clock, usually in steps of 1 MHz.

Adjusting the PCI Express reference clock changes its signalling rate and bandwidth. For example, increasing the reference clock frequency to 110 MHz would raise the PCI Express signalling rate by 10% to 2.75 gigatransfers/s (PCI Express 1.x) or 5.5 gigatransfers/s (PCI Express 2.0). However, because the PCI Express x16 interface already has such high bandwidth, overclocking it would only have a small effect on real world performance.

In motherboards that suffer from the PCI Express x1 bug, adjusting the reference clock speed up or down can potentially “trick” the motherboard to restore the PCI Express slot to its full x16 mode. However, raising the PCI Express reference clock to 120 MHz can cause timing-sensitive PCI Express devices like SATA controllers to fail. Therefore, it is recommended that you do not exceed 115 MHz, should you choose to overclock the PCI Express reference clock.

Go Back To > The Tech ARP BIOS Guide | Home

 

Support Tech ARP!

If you like our work, you can help support our work by visiting our sponsors, participating in the Tech ARP Forums, or even donating to our fund. Any help you can render is greatly appreciated!


Comments

comments

About The Author

Related posts

Leave a Reply

%d bloggers like this: