AGP Secondary Lat Timer from The Tech ARP BIOS Guide

AGP Secondary Lat Timer from The Tech ARP BIOS Guide

AGP Secondary Lat Timer

Common Options : 00h, 20h, 40h, 60h, 80h, C0h, FFh

 

Quick Review of AGP Secondary Lat Timer

The AGP Secondary Lat Timer BIOS feature controls how long the AGP bus can hold the PCI bus (via the PCI-to-PCI bridge) before another PCI device takes over. The longer the latency, the longer the AGP bus can retain control of the PCI bus before handing it over to another PCI device.

Normally, the AGP Secondary Latency Timer is set to 20h (32 clock cycles). This means the AGP bus’ PCI-to-PCI bridge has to complete its transactions within 32 clock cycles or hand it over to the next PCI device.

For better AGP performance, a longer latency should be used. Try increasing it to 40h (64 cycles) or even 80h (128 cycles). The optimal value for every system is different. You should benchmark your AGP card’s performance after each change to determine the optimal latency for your system.

If you set the AGP Secondary Latency Timer to a very large value like 80h (128 cycles) or C0h (192 cycles), it is recommended that you set the PCI Latency Time to 32 cycles. This provides better access for your PCI devices that might be unnecessarily stalled if both the AGP and PCI buses have very long latencies.

In addition, some time-critical PCI devices may not agree with a long AGP latency. Such devices require priority access to the PCI bus which may not be possible if the PCI bus is held up by the AGP bus for a long period. In such cases, it is recommended that you keep to the default latency of 20h (32 clock cycles).

 

Details of AGP Secondary Lat Timer

A bridge is a device that connects a primary bus with one or more logical secondary buses. The AGP bus is, therefore, a secondary bus connected to the PCI bus via a PCI-to-PCI bridge.

This BIOS feature is similar to the PCI Latency Timer BIOS feature. The only difference is this latency timer applies to the AGP bus, which is a secondary bus connected to the PCI bus via a PCI-to-PCI bridge. However, it is unknown why they named this BIOS feature AGP Secondary Lat Timer, instead of the more appropriate AGP Latency Timer or even PCI Secondary Latency Timer. The name is both misleading and inaccurate since the AGP bus does not have a secondary latency timer!

The AGP Secondary Lat Timer BIOS feature controls how long the AGP bus can hold the PCI bus (via the PCI-to-PCI bridge) before another PCI device takes over. The longer the latency, the longer the AGP bus can retain control of the PCI bus before handing it over to another PCI device.

Because a bridge device introduces additional delay to every transaction, a short latency would further reduce the amount of time the AGP bus has access to the PCI bus. A longer latency will allow the AGP bus more time to transact on the PCI bus. This speeds up AGP-to-PCI transactions.

Options (Hex)

Actual Latency

00h

0

20h

32

40h

64

60h

96

80h

128

C0h

192

FFh

255

The available options range are usually stated in terms of hexadecimal numbers. Here is a translation of those numbers into actual latencies :

Normally, the AGP Secondary Latency Timer is set to 20h (32 clock cycles). This means the AGP bus’ PCI-to-PCI bridge has to complete its transactions within 32 clock cycles or hand it over to the next PCI device.

For better AGP performance, a longer latency should be used. Try increasing it to 40h (64 cycles) or even 80h (128 cycles). The optimal value for every system is different. You should benchmark your AGP card’s performance after each change to determine the optimal latency for your system.

Please note that a longer latency isn’t necessarily better. A long latency can reduce performance as the other PCI devices queuing up may be stalled for too long. This is especially true with systems with many PCI devices or PCI devices that continuously write short bursts of data to the PCI bus. Such systems would work better with shorter latencies as they allow quicker access to the PCI bus.

Therefore, if you set the AGP Secondary Latency Timer to a very large value like 80h (128 cycles) or C0h (192 cycles), it is recommended that you set the PCI Latency Time to 32 cycles. This provides better access for your PCI devices that might be unnecessarily stalled if both the AGP and PCI buses have very long latencies.

In addition, some time-critical PCI devices may not agree with a long AGP latency. Such devices require priority access to the PCI bus which may not be possible if the PCI bus is held up by the AGP bus for a long period. In such cases, it is recommended that you keep to the default latency of 20h (32 clock cycles).

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