AGP 3.0 Calibration Cycle – BIOS Optimization Guide

AGP 3.0 Calibration Cycle

Common Options : Enabled, Disabled

 

Quick Review

This BIOS feature controls the AGP 3.0 calibration cycle feature of the motherboard chipset. It is only found in motherboards that support the AGP 3.0 standard.

When enabled, the motherboard chipset will periodically initiate a dynamic calibration cycle on the AGP bus. This allows the AGP bus to maintain its timings and signal integrity.

When disabled, the motherboard chipset will not initiate any dynamic calibration cycle on the AGP bus. The AGP bus timings and signal integrity may suffer from changes in voltage and temperature during operation.

As the dynamic calibration cycle maintains the AGP 3.0 bus’ timings and signal integrity, it is highly recommended that you leave it at the default setting of Enabled.

However, please note that this feature is only implemented if both motherboard chipset and AGP graphics card are operating in the AGP 3.0 mode. It is automatically disabled when the AGP 2.0 mode is used.

 

Details

The AGP 3.0 signaling scheme has very tight tolerances for its high-speed, source-synchronous signals which include the AD (data) bus and DBI (Dynamic Bus Inversion) signals. Unfortunately, key parameters like termination impedence, signal swing and slew rate can change due to changes in voltage and temperature during operation. These variations in key parameters can affect timing and signal integrity.

[adrotate banner=”4″]Therefore, the AGP 3.0 standard includes support for a dynamic calibration cycle. This feature allows the AGP 3.0 bus to dynamically recalibrate its source-synchronous signals over time.

The dynamic calibration cycle is periodically initiated by the motherboard chipset. By default, the AGP bus undergoes a dynamic calibration cycle every 4 ms. But the period between calibrations may be extended up to 256 ms, depending on motherboard implementation.

When a dynamic calibration cycle occurs, the chipset takes control of the AGP bus and initializes the dynamic calibration cycle. This takes three or more clock cycles to complete. Thereafter, the bus is released and a new AGP transaction may begin.

This BIOS feature controls the AGP 3.0 calibration cycle feature of the motherboard chipset. It is only found in motherboards that support the AGP 3.0 standard.

When enabled, the motherboard chipset will periodically initiate a dynamic calibration cycle on the AGP bus. This allows the AGP bus to maintain its timings and signal integrity.

When disabled, the motherboard chipset will not initiate any dynamic calibration cycle on the AGP bus. The AGP bus timings and signal integrity may suffer from changes in voltage and temperature during operation.

As the dynamic calibration cycle maintains the AGP 3.0 bus’ timings and signal integrity, it is highly recommended that you leave it at the default setting of Enabled.

However, please note that this feature is only implemented if both motherboard chipset and AGP graphics card are operating in the AGP 3.0 mode. It is automatically disabled when the AGP 2.0 mode is used.

 

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