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 05 August 2008
 Intel
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 Technology Report
 Dr. Adrian Wong
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The Intel Larrabee Processor Tech Report
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A Paradigm Shift?

On August 12, 2008, Intel will be presenting a paper on their future "many-core" processor architecture at SIGGRAPH 2008 in Los Angeles. Codenamed Larrabee, the new architecture will be highly scalable (many cores) and feature a new approach to 3D graphics rendering.

Yes, you read that right. Larrabee will introduce a new software rendering model for 3D graphics. In other words, Larrabee will mark Intel's first serious foray into 3D graphics since their last discrete graphics chip, the Intel i740.

However, Larrabee will be quite different from current discrete 3D graphics solutions in the sense it is a software solution based on the many-core Intel Larrabee processor. It is not a separate graphics chip. If Intel Larrabee works as predicted, the days of discrete graphics may be limited.

With that said, the first processor based on the Larrabee architecture will not be available until late 2009 or early 2010. So don't start selling your ATI Radeon or NVIDIA GeForce graphics cards yet!

 

Larrabee's Key Features

We will go through the Larrabee architecture in the following pages, but here are some of its features :

  • The Larrabee architecture has a pipeline derived from the dual-issue Intel Pentium® processor, which uses a short execution pipeline with a fully coherent cache structure. The Larrabee architecture provides significant modern enhancements such as a wide vector processing unit (VPU), multi-threading, 64-bit extensions and sophisticated pre-fetching. This will enable a massive increase in available computational power combined with the familiarity and ease of programming of the Intel architecture.
     
  • Larrabee also includes a select few fixed function logic blocks to support graphics and other applications. These units are carefully chosen to balance strong performance per watt, yet contribute to the flexibility and programmability of the architecture.
     
  • A coherent on-die 2nd level cache allows efficient inter-processor communication and high-bandwidth local data to be access by CPU cores, making the writing of software programs simpler.
     
  • The Larrabee native programming model supports a variety of highly parallel applications, including those that use irregular data structures. This enables development of graphics APIs, rapid innovation of new graphics algorithms, and true general purpose computation on the graphics processor with established PC software development tools.
     
  • Larrabee features task scheduling which is performed entirely with software, rather than in fixed function logic. Therefore rendering pipelines and other complex software systems can adjust their resource scheduling based each workload’s unique computing demand.
     
  • The Larrabee architecture supports four execution threads per core with separate register sets per thread. This allows the use of a simple efficient in-order pipeline, but retains many of the latency-hiding benefits of more complex out-of-order pipelines when running highly parallel applications.
     
  • The Larrabee architecture uses a 1024 bits-wide, bi-directional ring network (i.e., 512 bits in each direction) to allow agents to communicate with each other in low latency manner resulting in super fast communication between cores.
     
  • The Larrabee architecture fully supports IEEE standards for single and double precision floating-point arithmetic. Support for these standards is a pre-requisite for many types of tasks including financial applications.

Let's take a look at the Larrabee architecture.

 

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Page

Topic

1

A Paradigm Shift?
Larrabee's Key Features

2

A Convergence Of CPU + GPU?
Why Many Cores?

3

Inside The Larrabee
The Basic Core Design

4

The Larrabee Texture Sampler
How Does It Differ From A GPU?

5

How Larrabee Renders Graphics
Performance Scalability

6

The Larrabee Binning Renderer

7

Examples Of 3D Features Supported By Larrabee

8

Conclusion



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