DRAM Act to PreChrg CMD
Common Options : 5T, 6T, 7T, 8T, 9T
Like SDRAM Tras Timing Value, this BIOS feature controls the memory bank's minimum row active time (tRAS). This constitutes the time when a row is activated until the time the same row can be deactivated. Hence, the name DRAM Act to PreChrg CMD which is short for DRAM Activate Command to Precharge Command.
If the tRAS period is too long, it can reduce performance by unnecessarily delaying the deactivation of active rows. Reducing the tRAS period allows the active row to be deactivated earlier.
However, if the tRAS period is too short, there may not be enough time to complete a burst transfer. This reduces performance and data may be lost or corrupted.
For optimal performance, use the lowest value you can. Usually, this should be CAS latency + tRCD + 2 clock cycles. For example, if you set the CAS latency to 2 clock cycles and the tRCD to 3 clock cycles, the optimum tRAS value would be 7 clock cycles.
But if you start getting memory errors or system crashes, increase the tRAS value one clock cycle at a time until your system becomes stable.
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