DQS Training Control
Common Options : Perform DQS, Skip DQS
For proper memory reads to occur, the data strobes (DQS) must be properly timed to align with the data valid window of the data (DQ) lines. The data valid window refers to the specific period of time when the DRAM chip drives (makes active) the DQ lines for the memory controller to read its data.
This DQ-DQS timings are usually set by the motherboard designer after timing analyses using SPICE (Simulation Program for Integrated Circuit Emphasis). However, this approach is not foolproof as it is based on a particular set of hardware. The optimal DQ-DQS timings may vary for different hardware combinations. This is where the DQS Training Control BIOS feature comes in.
When set to Perform DQS, the chipset performs DQ-DQS calibration when the motherboard initializes. This ensures the DQS strobe is optimally aligned with the center of the data valid window of the DQ lines.
When set to Skip DQS, the chipset will not perform any DQ-DQS calibration when the motherboard initializes. It will use the default DQ-DQS timings.
Generally, such boot-time calibration is not necessary. The default DQ-DQS timings set by the motherboard designer will work for most memory configurations and clock speeds. Performing DQS training will not provide any benefit to either performance or stability. It will only introduce some boot-time delay, which may or may not be significant.
DQS training is only important if you intend to overclock the memory modules, or use memory modules that do not conform to JEDEC specifications (e.g. DDR2-1333 memory modules). The boot-time calibration will ensure proper alignment of the DQ-DQS signals for non-standard clock speeds, or memory modules.
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