K7 CLK_CTL Select
Common Options : Default, Optimal
As the name suggests, this is an AMD-specific BIOS feature. It controls the Clock Control (CLK_CTL) Model Specific Register (MSR) which is part of the AMD Athlon's power management control system.
Unlike the Intel Pentium 4 processor, the AMD Athlon processor saves power by actually reducing its internal clock speed. The Athlon bus clock speed remains constant but by using an internal clock divider, the Athlon processor can reduce its internal clock speed to 1/64th (Palomino cores and older) or 1/8th (Thoroughbred cores and newer) of its nominal clock speed.
The older Athlons have a bug (Errata No. 11) called PLL Overshoot on Wake-Up from Disconnect Causes Auto-Compensation Circuit to Fail. What happens is the processor can sometimes overshoot the nominal clock speed when it ramps up after a power-saving session. This causes a reduction in the Athlon bus' I/O drive strength levels which the auto-compensation circuitry will attempt to correct. But because there is not enough time, the proper drive strengths cannot be attained before the processor reconnects to the system bus. This causes the system bus to fail, which results in a system hang.
This bug is particularly prominent in the older Athlons that use the 1/64 internal divider because they normally require a longer ramp-up time which increases the chance for the processor to overshoot the nominal clock speed. Hence, a workaround for this bug was devised whereupon the BIOS will manually reprogram the CLK_CTL register to reduce the ramp-up time.
By default, the BIOS programs the CLK_CTL register with a value of 6003_1223h during the POST routine. To increase the ramp-up speed, the BIOS has to change the value to 2003_1223h.
This is where the K7 CLK_CTL Select BIOS feature comes in. When set to Default, the BIOS will program the CLK_CTL register with a value of 6003_1223h. Setting to Optimal causes the BIOS to program the CLK_CTL register with a value of 2003_1223h.
If you are using an AMD Athlon processor with a Palomino or older core, it is recommended that you set K7 CLK_CTL Select to Optimal. This will prevent Errata No. 11 from manifesting itself and may even provide a speed boost by allowing the processor to disconnect and connect to the system bus faster.
From the Thoroughbred-A core (CPUID 680) onwards, AMD started using an internal clock divider of only 1/8 with the CLK_CTL value of 6003_1223h. This neatly circumvents the Errata No. 11 problem although AMD also corrected that bug. With such processors, the CLK_CTL should be set to the Default value of 6003_1223h.
Unfortunately, AMD then did an about-turn with the Thoroughbred-B core (CPUID 681) and changed the value associated with the 1/8 divider from 6003_1223h to 2003_1223h. Unless the BIOS was updated to recognize this difference, it would probably write the 6003_1223h value used for the Thoroughbred-A core into the register, instead of the correct 2003_1223h required by the Thoroughbred-B core. When this happens, the processor may become unstable during transitions from sleep mode to active mode.
Therefore, for Throughbred-B cores and above, you should set the K7 CLK_CTL Select BIOS feature to Optimal setting to ensure proper setting of the internal clock divider.
Support Tech ARP!
Click here to find out how you can do that now!
Links: Discuss BIOS options here in our forums | Back to the list of BIOS options