SDRAM Burst Len – BIOS Optimization Guide

SDRAM Burst Len - BIOS Optimization Guide

SDRAM Burst Len

Common Options : 4, 8

 

Quick Review

This BIOS feature allows you to control the length of a burst transaction.

When this feature is set to 4, a burst transaction can only comprise of up to four reads or four writes.

When this feature is set to 8, a burst transaction can only comprise of up to eight reads or eight writes.

As the initial CAS latency is fixed for each burst transaction, a longer burst transaction will allow more data to be read or written for less delay than a shorter burst transaction. Therefore, a burst length of 8 will be faster than a burst length of 4.

Therefore, it is recommended that you select the longer burst length of 8 for better performance.

 

Details

This is the same as the SDRAM Burst Length BIOS feature, only with a weirdly truncated name. Surprisingly, many manufacturers are using it. Why? Only they know. ūüôā

Burst transactions improve SDRAM performance by allowing the reading or writing of whole ‘blocks’ of contiguous data with only one column address.

In a burst sequence, only the first read or write transfer incurs the initial latency of activating the column. The subsequent reads or writes in that burst sequence can then follow behind without any further delay. This allows blocks of data to be read or written with far less delay than non-burst transactions.

For example, a burst transaction of four writes can incur the following latencies : 4-1-1-1. In this example, the total time it takes to transact the four writes is merely 7 clock cycles.

In contrast, if the four writes are not written by burst transaction, they will incur the following latencies : 4-4-4-4. The time it takes to transact the four writes becomes 16 clock cycles, which is 9 clock cycles longer or more than twice as slow as a burst transaction.

This is where the SDRAM Burst Len BIOS feature comes in. It is a BIOS feature that allows you to control the length of a burst transaction.

When this feature is set to 4, a burst transaction can only comprise of up to four reads or four writes.

When this feature is set to 8, a burst transaction can only comprise of up to eight reads or eight writes.

As the initial CAS latency is fixed for each burst transaction, a longer burst transaction will allow more data to be read or written for less delay than a shorter burst transaction. Therefore, a burst length of 8 will be faster than a burst length of 4.

For example, if the memory controller wants to write a block of contiguous data eight units long to memory, it can do it as a single burst transaction 8 units long or two burst transactions, each 4 units in length. The hypothetical latencies incurred by the single 8-unit long transaction would be 4-1-1-1-1-1-1-1 with a total time of 11 clock cycles for the entire transaction.

But if the eight writes are written to memory as two burst transactions of 4 units in length, the hypothetical latencies incurred would be 4-1-1-1-4-1-1-1. The time taken for the two transactions to complete would be 14 clock cycles. As you can see, this is slower than a single transaction, 8 units long.

Therefore, it is recommended that you select the longer burst length of 8 for better performance.

 

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