K7 CLK_CTL Select – The BIOS Optimization Guide

K7 CLK_CTL Select - The BIOS Optimization Guide

K7 CLK_CTL Select

Common Options : Default, Optimal

 

Quick Review

As the name suggests, this is an AMD-specific BIOS feature. It controls the Clock Control (CLK_CTL) Model Specific Register (MSR) which is part of the AMD Athlon’s power management control system.

The older Athlons have a bug that causes the system to hang, when the processor overshoots the nominal clock speed while recovering from a power-saving session. Hence, a workaround for this bug was devised whereupon the BIOS will manually reprogram the CLK_CTL register to reduce the ramp-up time.

By default, the BIOS programs the CLK_CTL register with a value of 6003_1223h during the POST routine. To increase the ramp-up speed, the BIOS has to change the value to 2003_1223h.

This is where the K7 CLK_CTL Select BIOS feature comes in. When set to Default, the BIOS will program the CLK_CTL register with a value of 6003_1223h. Setting to Optimal causes the BIOS to program the CLK_CTL register with a value of 2003_1223h.

If you are using an AMD Athlon processor with a Palomino or older core, it is recommended that you set K7 CLK_CTL Select to Optimal. This will prevent the bug from manifesting itself and may even provide a speed boost by allowing the processor to disconnect and connect to the system bus faster.

From the Thoroughbred-A core (CPUID 680) onwards, AMD started using an internal clock divider of only 1/8 with the CLK_CTL value of 6003_1223h. This neatly circumvents the Errata No. 11 problem, although AMD also corrected that bug. With such processors, the CLK_CTL should be set to the Default value of 6003_1223h.

Unfortunately, AMD then did an about-turn with the Thoroughbred-B core (CPUID 681) and changed the value associated with the 1/8 divider from 6003_1223h to 2003_1223h. Unless the BIOS was updated to recognize this difference, it would probably write the 6003_1223h value used for the Thoroughbred-A core into the register, instead of the correct 2003_1223h required by the Thoroughbred-B core. When this happens, the processor may become unstable during transitions from sleep mode to active mode.

Therefore, for Throughbred-B cores and above, you should set the K7 CLK_CTL Select BIOS feature to Optimal setting to ensure proper setting of the internal clock divider.

 

Details

As the name suggests, this is an AMD-specific BIOS feature. It controls the Clock Control (CLK_CTL) Model Specific Register (MSR) which is part of the AMD Athlon’s power management control system.

First of all, we should be aware that the AMD Athlon family of processors has four different power management states :-

Working State (C0)
Halt State (C1)
Stop Grant States (C2 and S1)
Probe State

The Athlon processor can switch to its power-saving mode when it is in the Halt state or one of the Stop Grant states. In those power management states, the processor will send a HLT or STPCLK# special bus cycle to the north bridge which disconnects the Athlon system bus. The processor will then enter into its power saving mode.

Unlike the Intel Pentium 4 processor, the AMD Athlon processor saves power by actually reducing its internal clock speed. The Athlon bus clock speed remains constant but by using an internal clock divider, the Athlon processor can reduce its internal clock speed to 1/64th (Palomino cores and older) or 1/8th (Thoroughbred cores and newer) of its nominal clock speed. That means a 2.0GHz Athlon processor with a Palomino or older core will have an internal clock speed of only 31.25 MHz in power saving mode! But if the same processor has a Thoroughbred core, the internal clock speed in power saving mode will be 250 MHz.

As you can see, the older Athlon cores run at a much lower internal speed compared to the newer cores. This translates into a much lower power consumption in power-saving modes. For example, Athlon processors with Palomino cores use only 0.86 W of power in power saving mode. In contrast, the newer Athlon Thoroughbred-B processors in power saving mode will consume about 8.9 W of power. However, the extremely low internal clock speed in the older Athlon cores meant that these cores will take a much longer time to ramp up to full clock speed when it “awakes” from its power saving mode. This can sometimes cause problems.

The older Athlons have a bug (Errata No. 11) called PLL Overshoot on Wake-Up from Disconnect Causes Auto-Compensation Circuit to Fail. What happens is the processor can sometimes overshoot the nominal clock speed when it ramps up after a power-saving session. This causes a reduction in the Athlon bus’ I/O drive strength levels which the auto-compensation circuitry will attempt to correct. But because there is not enough time, the proper drive strengths cannot be attained before the processor reconnects to the system bus. This causes the system bus to fail, which results in a system hang.

This bug is particularly prominent in the older Athlons that use the 1/64 internal divider because they normally require a longer ramp-up time which increases the chance for the processor to overshoot the nominal clock speed. Hence, a workaround for this bug was devised whereupon the BIOS will manually reprogram the CLK_CTL register to reduce the ramp-up time. With a reduced ramp-up time, there will be very little chance of the processor overshooting and causing a failure of the system bus.

By default, the BIOS programs the CLK_CTL register with a value of 6003_1223h during the POST routine. To increase the ramp-up speed, the BIOS has to change the value to 2003_1223h.

This is where the K7 CLK_CTL Select BIOS feature comes in. When set to Default, the BIOS will program the CLK_CTL register with a value of 6003_1223h. Setting to Optimal causes the BIOS to program the CLK_CTL register with a value of 2003_1223h.

If you are using an AMD Athlon processor with a Palomino or older core, it is recommended that you set K7 CLK_CTL Select to Optimal. This will prevent Errata No. 11 from manifesting itself and may even provide a speed boost by allowing the processor to disconnect and connect to the system bus faster.

From the Thoroughbred-A core (CPUID 680) onwards, AMD started using an internal clock divider of only 1/8 with the CLK_CTL value of 6003_1223h. While this means that the newer cores will consume more power during power-saving states, the 1/8 divider allows a much faster ramp-up time. This neatly circumvents the Errata No. 11 problem although AMD also corrected that bug. With such processors, the CLK_CTL should be set to the Default value of 6003_1223h.

Unfortunately, AMD then did an about-turn with the Thoroughbred-B core (CPUID 681) and changed the value associated with the 1/8 divider from 6003_1223h to 2003_1223h. Unless the BIOS was updated to recognize this difference, it would probably write the 6003_1223h value used for the Thoroughbred-A core into the register, instead of the correct 2003_1223h required by the Thoroughbred-B core. When this happens, the processor may become unstable during transitions from sleep mode to active mode.

Therefore, for Throughbred-B cores and above, you should set the K7 CLK_CTL Select BIOS feature to Optimal setting to ensure proper setting of the internal clock divider.

 

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