Data Prefetch Logic – BIOS Optimization Guide

Data Prefetch Logic - BIOS Optimization Guide

Data Prefetch Logic

Common Options : Enabled, Disabled

 

Quick Review

The processor has a hardware prefetcher that automatically analyzes its requirements and prefetches data and instructions from the memory into the Level 2 cache that are likely to be required in the near future. This reduces the latency associated with memory reads.

When enabled, the processor’s hardware prefetcher will be enabled and allowed to automatically prefetch data and code for the processor.

When disabled, the processor’s hardware prefetcher will be disabled.

It is recommended that you enable this BIOS feature so that the hardware prefetcher is enabled for maximum performance.

 

Details

This is a BIOS feature specific to processors based on the Intel Core microarchitecture (e.g. Intel Core i7, Core i5, Core i3).

These processors have a hardware prefetcher (officially known as the Data Prefetch Logic or DPL) that automatically analyzes the processor’s requirements and prefetches data and instructions from the memory into the Level 2 cache that are likely to be required in the near future. This reduces the latency associated with memory reads.

When enabled, the processor’s hardware prefetcher will be enabled and allowed to automatically prefetch data and code for the processor.

When disabled, the processor’s hardware prefetcher will be disabled.

It is recommended that you enable this BIOS feature so that the hardware prefetcher is enabled for maximum performance.

 

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